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74LVC1G06 Datasheet(PDF) 1 Page - NXP Semiconductors |
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74LVC1G06 Datasheet(HTML) 1 Page - NXP Semiconductors |
1 / 14 page 1. General description The 74LVC1G06 provides the inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. 2. Features s Wide supply voltage range from 1.65 V to 5.5 V s High noise immunity s Complies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8B/JESD36 (2.7 V to 3.6 V) s ±24 mA output drive (V CC = 3.0 V) s CMOS low power consumption s Latch-up performance exceeds 250 mA s Direct interface with TTL levels s Inputs accept voltages up to 5 V s Multiple package options s ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A115-A exceeds 200 V s Specified from −40 °C to +125 °C 74LVC1G06 Inverter with open-drain output Rev. 07 — 12 July 2007 Product data sheet |
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