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74LVC169 Datasheet(PDF) 7 Page - NXP Semiconductors |
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74LVC169 Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 22 page 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 7 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter The following sequence is illustrated: - Load (preset) to thirteen. - Count up to fourteen, fifteen (maximum), zero, one and two. - Inhibit. - Countdown to one, zero (minimum), fifteen, fourteen and thirteen. Fig 7. Typical timing sequence 001aaa648 U/D D0 TC PE inhibit count down count up load CEP and CET D1 D3 D2 CP Q0 Q2 Q1 Q3 13 14 15 0 1 2 2 2 1 0 14 15 13 |
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