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74LVTH16374ADGG Datasheet(PDF) 11 Page - NXP Semiconductors |
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74LVTH16374ADGG Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 19 page 74LVT_LVTH16374A_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 22 March 2010 11 of 19 NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state Test data is given in Table 9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 10. Test circuit for measuring switching times VEXT VCC VI VO 001aae235 DUT CL RT RL RL PULSE GENERATOR VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf Table 9. Test data Input Load VEXT VI fi tW tr, tf CL RL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 2.7 V ≤ 10 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω GND 6 V open |
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