ADC1412D065 datasheet(1/37 Pages) NXP

Part #	ADC1412D065

Description	Dual 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs

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Manufacturer	NXP [NXP Semiconductors]

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1.

General description

The ADC1412D is a dual channel 14-bit Analog-to-Digital Converter (ADC) optimized for

high dynamic performances and low power consumption at sample rates up to 125 Msps.

Pipelined architecture and output error correction ensure the ADC1412D is accurate

enough to guarantee zero missing codes over the entire operating range. Supplied from a

single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,

thanks to a separate digital output supply. It supports the LVDS (Low Voltage Differential

Signalling) DDR (Double Data Rate) output standard. An integrated SPI (Serial Peripheral

Interface) allows the user to easily conﬁgure the ADC. The device also includes a

programmable gain ampliﬁer with a ﬂexible input voltage range. With excellent dynamic

performance from the baseband to input frequencies of 170 MHz or more, the ADC1412D

is ideal for use in communications, imaging and medical applications.

2.

Features

ADC1412D065/080/105/125

Dual 14-bit ADC 65, 80, 105 or 125 Msps

CMOS or LVDS DDR digital outputs

Rev. 02 — 4 June 2009

Objective data sheet

Fig 1.

Integral Non-Linearity (INL)

Fig 2.

Differential Non-Linearity

(DNL)

Fig 3.

Output spectrum:

−1 dBFS,

80 Msps, fi = 4.43 MHz

0

16000

12000

4000

8000

005aaa040

-0.5

-1

0.5

0

1.5

1

-1.5

0

16000

12000

4000

8000

005aaa041

-0.5

0.5

1

-1

0

1.5

-1.5

f (MHz)

040

30

10

20

005aaa042

-80

-40

0

dB

-120

I SNR, 73 dB

I Input bandwidth, 650 MHz

I SFDR, 90 dBc

I Power dissipation, 775 mW at 80 Msps

I Sample rate up to 125 Msps

I SPI Interface

I Dual-channel14-bit pipelined ADC core I Duty cycle stabilizer

I Single 3 V supply

I Fast OTR detection

I Flexible input voltage range: 1 V to 2 V

(p-p) with 6 dB programmable ﬁne gain

I Offset binary, 2’s complement, gray

code

I CMOS or LVDS DDR digital outputs

I Power-down and Sleep modes

I INL ±1 LSB, DNL ±0.5 LSB (typical)

I HVQFN64 package

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