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ADC1415S Datasheet(PDF) 4 Page - NXP Semiconductors |
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ADC1415S Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 39 page ADC1415S_SER_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 12 April 2010 4 of 39 NXP Semiconductors ADC1415S series ADC1415S series; input buffer; CMOS or LVDS DDR digital outputs 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 2. Pin configuration with CMOS digital outputs selected Fig 3. Pin configuration with LVDS/DDR digital outputs selected 005aaa102 ADC1415S HVQFN40 D9 AGND VDDA3V D8 INP D7 INM D6 AGND D5 VDDA5V D4 VCM D3 AGND D2 REFT D1 REFB D0 10 21 9 22 8 23 7 24 6 25 5 26 4 27 3 28 2 29 1 30 terminal 1 index area Transparent top view ADC1215S HVQFN40 D8_D9_M D8_D9_P D6_D7_M D6_D7_P D4_D5_M D4_D5_P D2_D3_M D2_D3_P D0_D1_M D0_D1_P VDDA3V INP INM AGND VDDA5V VCM AGND REFT REFB 10 21 9 22 8 23 7 24 6 25 5 26 4 27 3 28 2 29 1 30 AGND terminal 1 index area Transparent top view 005aaa103 Table 2. Pin description (CMOS digital outputs) Symbol Pin Type [1] Description REFB 1 O bottom reference REFT 2 O top reference AGND 3 G analog ground VCM 4 O common-mode output voltage VDDA5V 5 P 5 V analog power supply AGND 6 G analog ground INM 7 I complementary analog input INP 8 I analog input AGND 9 G analog ground VDDA3V 10 P 3 V analog power supply VDDA3V 11 P 3 V analog power supply CLKP 12 I clock input CLKM 13 I complementary clock input DEC 14 O regulator decoupling node OE 15 I output enable, active LOW PWD 16 I power down, active HIGH |
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