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CS61884-IQZ Datasheet(PDF) 30 Page - Cirrus Logic |
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CS61884-IQZ Datasheet(HTML) 30 Page - Cirrus Logic |
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30 / 71 page  CS61884 30 DS485F1 12.3 Digital Loopback Digital Loopback causes the TCLK, TPOS, and TNEG (or TDATA) inputs to be looped back through the jitter attenuator (if enabled) to the RCLK, RPOS, and RNEG (or RDATA) outputs. The receive line interface is ignored, but data at TPOS and TNEG (or TDATA) continues to be transmitted to the line interface at TTIP and TRING (Refer to Figure 10 on page 31). Digital Loopback is only available during host mode. It is selected using the appropriate bit in the Digital Loopback Reset Register (0Ch) (See Sec- tion 14.13 on page 37). NOTE: TAOS can also be used during the Digital Loop- back operation for the selected channel (Refer to Figure 11 on page 31). 12.4 Remote Loopback In remote loopback, the RPOS/RNEG and RCLK outputs are internally input to the transmit circuits for output on TTIP/TRING. In this mode the TCLK, TPOS and TNEG inputs are ignored. (Refer to Figure 12 on page 31). In hardware mode, Re- mote Loopback is selected by driving the LOOP pin for a certain channel low. In host mode, Remote Loopback is selected for a given channel by writing a one to the appropriate bit in the Remote Loop- back Register (02h) (See Section 14.3 on page 35). NOTE: In hardware mode, Remote Loopback over- rides TAOS for the selected channel. In host mode, TAOS overrides Remote Loopback. TTIP TRING RTIP RRING TNEG TCLK RNEG RCLK TPOS RPOS Clock Recovery & Data Recovery Transmit Control & Pulse Shaper Figure 8. Analog Loopback Block Diagram TNEG TCLK RNEG RCLK TPOS RPOS TAOS MCLK (All One's) TTIP TRING RTIP RRING Clock Recovery & Data Recovery Transmit Control & Pulse Shaper Figure 9. Analog Loopback with TAOS Block Diagram |
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