CS4228A

8

Notes: 14. See Cl1:0 register on page 22 for settings.

15. After powering up the CS4228A, RST should be held low for 1 ms after the power supplies and clocks

are settled.

16. Scales with sample rate Fs. 50 ns valid at 48 kHz, more time at slower Fs and less time at faster Fs.

17. See DCK1:0 register on page 25 for settings.

Parameter

Symbol

Min

Typ

Max

Units

Audio ADC's and DAC's Sample Rate

BRM

HRM

Fs

30

60

-

-

50

100

kHz

kHz

MCLK Frequency

(Note 14)

3.84

-

25.6

MHz

MCLK Duty Cycle

BRM

MCLK =128, 384 Fs

MCLK = 256, 512 Fs

HRM

MCLK = 64, 192 Fs

MCLK = 128, 256 Fs

40

40

40

40

50

50

50

50

60

60

60

60

%

%

%

%

RST Low Time

(Note 15)

1-

-

ms

SCLK Falling Edge to SDOUT Output Valid

(Note 16)

-50

ns

LRCK Edge to MSB Valid

-20

ns

SDIN Setup Time Before SCLK Rising Edge

-10

ns

SDIN Hold Time After SCLK Rising Edge

-30

ns

SCLK Period BRM

(Note 17)

--

ns

SCLK Period HRM

(Note 17)

--

ns

Master Mode

SCLK Falling to LRCK Edge

+10

-

ns

SCLK Duty Cycle

50

-

%

Slave Mode

SCLK High Time

50

-

-

ns

SCLK Low Time

50

-

-

ns

SCLK rising to LRCK Edge

25

-

-

ns

LRCK Edge to SCLK Rising

25

-

-

ns

1

128

()Fs

----------------------

1

64

()Fs

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