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CS4228A Datasheet(PDF) 8 Page - Cirrus Logic |
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CS4228A Datasheet(HTML) 8 Page - Cirrus Logic |
8 / 32 page CS4228A 8 SWITCHING CHARACTERISTICS (Inputs: Logic 0 = 0V, Logic 1 = VL) Notes: 14. See Cl1:0 register on page 22 for settings. 15. After powering up the CS4228A, RST should be held low for 1 ms after the power supplies and clocks are settled. 16. Scales with sample rate Fs. 50 ns valid at 48 kHz, more time at slower Fs and less time at faster Fs. 17. See DCK1:0 register on page 25 for settings. Parameter Symbol Min Typ Max Units Audio ADC's and DAC's Sample Rate BRM HRM Fs 30 60 - - 50 100 kHz kHz MCLK Frequency (Note 14) 3.84 - 25.6 MHz MCLK Duty Cycle BRM MCLK =128, 384 Fs MCLK = 256, 512 Fs HRM MCLK = 64, 192 Fs MCLK = 128, 256 Fs 40 40 40 40 50 50 50 50 60 60 60 60 % % % % RST Low Time (Note 15) 1- - ms SCLK Falling Edge to SDOUT Output Valid (Note 16) tdpd -50 ns LRCK Edge to MSB Valid tlrpd -20 ns SDIN Setup Time Before SCLK Rising Edge tds -10 ns SDIN Hold Time After SCLK Rising Edge tdh -30 ns SCLK Period BRM (Note 17) tsck -- ns SCLK Period HRM (Note 17) tsck -- ns Master Mode SCLK Falling to LRCK Edge tmslr +10 - ns SCLK Duty Cycle 50 - % Slave Mode SCLK High Time tsckh 50 - - ns SCLK Low Time tsckl 50 - - ns SCLK rising to LRCK Edge tlrckd 25 - - ns LRCK Edge to SCLK Rising tlrcks 25 - - ns 1 128 ()Fs ---------------------- 1 64 ()Fs ------------------ |
Similar Part No. - CS4228A_03 |
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Similar Description - CS4228A_03 |
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