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LM3S6911-EQR50-A2T Datasheet(PDF) 4 Page - Texas Instruments |
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LM3S6911-EQR50-A2T Datasheet(HTML) 4 Page - Texas Instruments |
4 / 514 page 6.1.2 Reset Control ................................................................................................................ 63 6.1.3 Power Control ............................................................................................................... 66 6.1.4 Clock Control ................................................................................................................ 68 6.1.5 System Control ............................................................................................................. 71 6.2 Initialization and Configuration ....................................................................................... 72 6.3 Register Map ................................................................................................................ 72 6.4 Register Descriptions .................................................................................................... 73 7 Hibernation Module .............................................................................................. 124 7.1 Block Diagram ............................................................................................................ 125 7.2 Functional Description ................................................................................................. 125 7.2.1 Register Access Timing ............................................................................................... 125 7.2.2 Clock Source .............................................................................................................. 126 7.2.3 Battery Management ................................................................................................... 127 7.2.4 Real-Time Clock .......................................................................................................... 127 7.2.5 Non-Volatile Memory ................................................................................................... 128 7.2.6 Power Control ............................................................................................................. 128 7.2.7 Initiating Hibernate ...................................................................................................... 128 7.2.8 Interrupts and Status ................................................................................................... 129 7.3 Initialization and Configuration ..................................................................................... 129 7.3.1 Initialization ................................................................................................................. 129 7.3.2 RTC Match Functionality (No Hibernation) .................................................................... 129 7.3.3 RTC Match/Wake-Up from Hibernation ......................................................................... 130 7.3.4 External Wake-Up from Hibernation .............................................................................. 130 7.3.5 RTC/External Wake-Up from Hibernation ...................................................................... 130 7.4 Register Map .............................................................................................................. 130 7.5 Register Descriptions .................................................................................................. 131 8 Internal Memory ................................................................................................... 144 8.1 Block Diagram ............................................................................................................ 144 8.2 Functional Description ................................................................................................. 144 8.2.1 SRAM Memory ............................................................................................................ 144 8.2.2 Flash Memory ............................................................................................................. 145 8.3 Flash Memory Initialization and Configuration ............................................................... 146 8.3.1 Flash Programming ..................................................................................................... 146 8.3.2 Nonvolatile Register Programming ............................................................................... 147 8.4 Register Map .............................................................................................................. 148 8.5 Flash Register Descriptions (Flash Control Offset) ......................................................... 149 8.6 Flash Register Descriptions (System Control Offset) ...................................................... 157 9 General-Purpose Input/Outputs (GPIOs) ........................................................... 170 9.1 Functional Description ................................................................................................. 170 9.1.1 Data Control ............................................................................................................... 171 9.1.2 Interrupt Control .......................................................................................................... 172 9.1.3 Mode Control .............................................................................................................. 173 9.1.4 Commit Control ........................................................................................................... 173 9.1.5 Pad Control ................................................................................................................. 173 9.1.6 Identification ............................................................................................................... 173 9.2 Initialization and Configuration ..................................................................................... 173 9.3 Register Map .............................................................................................................. 174 9.4 Register Descriptions .................................................................................................. 176 April 05, 2010 4 Texas Instruments-Production Data Table of Contents |
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