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LM3S6938-EQR20-A2 Datasheet(PDF) 9 Page - Texas Instruments |
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LM3S6938-EQR20-A2 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 559 page Figure 15-1. I2C Block Diagram ............................................................................................. 391 Figure 15-2. I2C Bus Configuration ........................................................................................ 391 Figure 15-3. START and STOP Conditions ............................................................................. 392 Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 392 Figure 15-5. R/S Bit in First Byte ............................................................................................ 392 Figure 15-6. Data Validity During Bit Transfer on the I2C Bus ................................................... 393 Figure 15-7. Master Single SEND .......................................................................................... 396 Figure 15-8. Master Single RECEIVE ..................................................................................... 397 Figure 15-9. Master Burst SEND ........................................................................................... 398 Figure 15-10. Master Burst RECEIVE ...................................................................................... 399 Figure 15-11. Master Burst RECEIVE after Burst SEND ............................................................ 400 Figure 15-12. Master Burst SEND after Burst RECEIVE ............................................................ 401 Figure 15-13. Slave Command Sequence ................................................................................ 402 Figure 16-1. Ethernet Controller ............................................................................................. 427 Figure 16-2. Ethernet Controller Block Diagram ...................................................................... 427 Figure 16-3. Ethernet Frame ................................................................................................. 428 Figure 16-4. Interface to an Ethernet Jack .............................................................................. 433 Figure 17-1. Analog Comparator Module Block Diagram ......................................................... 474 Figure 17-2. Structure of Comparator Unit .............................................................................. 475 Figure 17-3. Comparator Internal Reference Structure ............................................................ 475 Figure 18-1. 100-Pin LQFP Package Pin Diagram .................................................................. 485 Figure 18-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 486 Figure 21-1. Load Conditions ................................................................................................ 518 Figure 21-2. JTAG Test Clock Input Timing ............................................................................. 520 Figure 21-3. JTAG Test Access Port (TAP) Timing .................................................................. 521 Figure 21-4. JTAG TRST Timing ............................................................................................ 521 Figure 21-5. External Reset Timing (RST) .............................................................................. 522 Figure 21-6. Power-On Reset Timing ..................................................................................... 522 Figure 21-7. Brown-Out Reset Timing .................................................................................... 522 Figure 21-8. Software Reset Timing ....................................................................................... 522 Figure 21-9. Watchdog Reset Timing ..................................................................................... 523 Figure 21-10. Hibernation Module Timing ................................................................................. 524 Figure 21-11. ADC Input Equivalency Diagram ......................................................................... 525 Figure 21-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .................................................................................................... 526 Figure 21-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 526 Figure 21-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 527 Figure 21-15. I2C Timing ......................................................................................................... 528 Figure 21-16. External XTLP Oscillator Characteristics ............................................................. 530 Figure D-1. 100-Pin LQFP Package ...................................................................................... 555 Figure D-2. 108-Ball BGA Package ...................................................................................... 557 9 April 05, 2010 Texas Instruments-Production Data Stellaris® LM3S6938 Microcontroller |
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