ADS62C15_10 datasheet(5/64 Pages) TI

Part #	ADS62C15

Description	Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs

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ELECTRICAL CHARACTERISTICS

ADS62C15

www.ti.com....................................................................................................................................................... SLAS577D – JANUARY 2008 – REVISED JULY 2009

Typical values at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3

V, DRVDD = 1.8 V to 3.3 V, sampling frequency = 125 MSPS, 50% clock duty cycle, –1 dBFS differential analog input,

internal reference mode, SNRBoost disabled, applies to CMOS and LVDS interfaces (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

Resolution

11

bits

ANALOG INPUTS

Differential input voltage range

2

VPP

Differential input resistance (at dc)

See Figure 32

> 1

M

Ω

Differential input capacitance

See Figure 33

7

pF

Analog input bandwidth

450

MHz

Analog input common mode current (per

125

µA

input pin)

VCM common mode voltage output

1.5

V

VCM output current capability

4

mA

POWER SUPPLY

Analog supply current (AVDD)

216

ISS

mA

Output buffer supply current (DRVDD)

DRVDD = 1.8 V, 2.5 MHz input signal

17

CMOS interface

no load capacitance(1)

Total power – CMOS interface

0.74

W

DRVDD = 3.3 V, 50 MHz input signal

1.22

Total power – CMOS interface

W

10 pF load capacitance

5

Total power – LVDS interface

DRVDD = 3.3 V

0.94

W

Global power down

30

60

mW

DC ACCURACY

No missing codes

Specif

ied

DNL

Differential Non-Linearity

–0.8

±0.4

0.8

LSB

INL

Integral Non-Linearity

–3.5

±1

3.5

LSB

EO

Offset Error

–10

±3

10

mV

Offset error temperature coefficient

0.05

mV/°C

There are two sources of gain error – internal reference inaccuracy and channel gain error

Gain error due to internal reference

EGREF

–1

±0.25

1

%FS

inaccuracy alone

EGCHAN Gain error of channel alone

(2)

–1

±0.3

1

%FS

Channel gain error temperature

0.005

Δ%/°C

coefficient

(1)

In CMOS mode, the DRVDD current scales with the sampling frequency and the load capacitance on output pins (see Figure 29).

(2)

This is specified by design and characterization; it is not tested in production.

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