LM75A_4

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 04 — 10 July 2007

11 of 24

NXP Semiconductors

LM75A

Digital temperature sensor and thermal watchdog

When the power supply voltage is dropped below the device power-on reset level of

approximately 1.9 V (POR) and then rises up again, the device will be reset to its default

condition as listed above.

7.10 Protocols for writing and reading the registers

The communication between the host and the LM75A must strictly follow the rules as

operations are illustrated in Figure 5 to Figure 10 together with the following definitions:

and SDA lines must both be released by all devices on the bus, and they become

HIGH by the bus pull-up resistors.

2. The host must provide SCL clock pulses necessary for the communication. Data is

transferred in a sequence of 9 SCL clock pulses for every 8-bit data byte followed by

1-bit status of the acknowledgement.

3. During data transfer, except the START and STOP signals, the SDA signal must be

stable while the SCL signal is HIGH. It means that the SDA signal can be changed

only during the LOW duration of the SCL line.

4. S: START signal, initiated by the host to start a communication, the SDA goes from

HIGH to LOW while the SCL is HIGH.

5. RS: RE-START signal, same as the START signal, to start a read command that

follows a write command.

6. P: STOP signal, generated by the host to stop a communication, the SDA goes from

LOW to HIGH while the SCL is HIGH. The bus becomes free thereafter.

7. W: write bit, when the write/read bit = LOW in a write command.

8. R: read bit, when the write/read bit = HIGH in a read command.

9. A: device acknowledge bit, returned by the LM75A. It is LOW if the device works

properly and HIGH if not. The host must release the SDA line during this period in

order to give the device the control on the SDA line.

10. A’: master acknowledge bit, not returned by the device, but set by the master or host

in reading 2-byte data. During this clock period, the host must set the SDA line to

LOW in order to notify the device that the first byte has been read for the device to

provide the second byte onto the bus.

11. NA: Not Acknowledge bit. During this clock period, both the device and host release

the SDA line at the end of a data transfer, the host is then enabled to generate the

STOP signal.

12. In a write protocol, data is sent from the host to the device and the host controls the

SDA line, except during the clock period when the device sends the device

acknowledgement signal to the bus.

13. In a read protocol, data is sent to the bus by the device and the host must release the

SDA line during the time that the device is providing data onto the bus and controlling

the SDA line, except during the clock period when the master sends the master

acknowledgement signal to the bus.