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MC3S12Q96CFU8 Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc |
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MC3S12Q96CFU8 Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc |
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2 / 644 page  To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ A full list of family members and options is included in the appendices. The following revision history table summarizes changes contained in this document. This document contains information for all constituent modules, with the exception of the S12 CPU. For S12 CPU information please refer to the CPU S12 Reference Manual. Date Revision Level Description January 2006 01.05 Updated LVI levels in electrical parameter section Fixed incorrect reference to TSCR2 May 2006 01.06 Added 0M66G PART ID number Corrected missing overbars on pin names Added units to MSCAN timing table Dec 2006 01.07 Corrected CRGFLG contents in register summary Corrected unintended symbol font May 2007 01.08 Added emulation package info. Corrected TIM and PWM channel count in PIM section Updated ATD section Corrected typos and inconsistent register listing format Dec 2007 01.09 Added new PartID May 2010 01.10 Updated TIM section (see TIM rev. history) |
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