PCA9553_6

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 06 — 29 December 2008

5 of 26

NXP Semiconductors

PCA9553

7.

Functional description

Refer to Figure 1 “Block diagram”.

7.1 Device address

Following a START condition the bus master must output the address of the slave it is

accessing. The address of the PCA9553/01 is shown in Figure 5 and PCA9553/02 in

Figure 6.

PCA9553TK uses the version /01 address.

The last bit of the address byte defines the operation to be performed. When set to logic 1

a read is selected, while a logic 0 selects a write operation.

7.2 Control register

Following the successful acknowledgement of the slave address, the bus master will send

a byte to the PCA9553 which will be stored in the Control register.

The lowest 3 bits are used as a pointer to determine which register will be accessed.

If the Auto-Increment flag is set, the three low order bits of the Control register are

automatically incremented after a read or write. This allows the user to program the

registers sequentially. The contents of these bits will rollover to ‘000’ after the last register

is accessed.

When the Auto-Increment flag is set (AI = 1) and a read sequence is initiated, the

sequence must start by reading a register different from ‘0’ (B2 B1 B0

≠ 0 0 0).

Only the 3 least significant bits are affected by the AI flag.

Unused bits must be programmed with zeroes.

Fig 5.

PCA9553/01 slave address

Fig 6.

PCA9553/02 slave address

R/W

002aad742

1

1

0

0

0

1

0

slave address

R/W

002aad743

1

1

0

0

0

1

1

slave address

Reset state: 00h

Fig 7.

Control register

B0

002aad744

0

0

0

AI

0

B2

B1

register address

Auto-Increment

flag