PCA9557

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 06 — 11 June 2008

11 of 26

NXP Semiconductors

PCA9557

8.4 Bus transactions

Data is transmitted to the PCA9557 registers using Write Byte transfers (see Figure 14

and Figure 15). Data is read from the PCA9557 registers using Read and Receive Byte

transfers (see Figure 16 and Figure 17).

002aaa987

S

START

condition

9

8

2

1

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from master

Fig 14. Write to output port register

0

A

S

slave address

START condition

R/W

acknowledge

from slave

002aad281

0000001

0

command byte

A

acknowledge

from slave

12345678

SCL

9

SDA

DATA 1

A

write to port

data out from port

acknowledge

from slave

DATA 1 VALID

data to port

0

1

1

A2 A1 A0

0

P

STOP

condition

Fig 15. Write to I/O configuration or polarity inversion registers

0

A

S

slave address

START condition

R/W

acknowledge

from slave

002aad282

000001 1/0

0

command byte

A

acknowledge

from slave

12345678

SCL

9

SDA

DATA

A

acknowledge

from slave

data to register

0

1

1

A2 A1 A0

0

P

STOP

condition