PESDXU1UT_SER_2

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 02 — 20 August 2009

8 of 13

NXP Semiconductors

PESDxU1UT series

Ultra low capacitance ESD protection diode in SOT23 package

Circuit board layout and protection device placement

Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)

and surge transients. The following guidelines are recommended:

1. Place the PESDxU1UT as close to the input terminal or connector as possible.

2. The path length between the PESDxU1UT and the protected line should be

minimized.

3. Keep parallel signal paths to a minimum.

4. Avoid running protected conductors in parallel with unprotected conductors.

5. Minimize all printed-circuit board conductive loops including power and ground loops.

6. Minimize the length of the transient return path to ground.

7. Avoid using shared transient return paths to a common ground point.

8. Ground planes should be used whenever possible. For multilayer printed-circuit

boards, use ground vias.