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Si3461-KIT Datasheet(PDF) 9 Page - Silicon Laboratories |
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Si3461-KIT Datasheet(HTML) 9 Page - Silicon Laboratories |
9 / 24 page Si3461 Rev. 1.0 9 2.2. PSE Timing Characteristics When implemented in accordance with the recommended external components and layout guidelines, the Si3461 controller enables the following typical performance characteristics in single-port PSE applications. Refer to the Si3461-EVB applications note, schematics, and user's guide for more details. Table 5. PSE Timing Description Symbol Test Conditions Min Typ Max Unit Endpoint Detection Delay Cycle tDET_CYCLE Time from PD connection to port to completion of detection process. 90 — 460 ms Detection Time tDETECT Time required to measure PD signature resistance. — 90 — ms Classification Delay Cycle tCLASS_CYCLE Class 0/1/2/3; Time from successful detect mode to classification complete. — 60 — ms Class 4, two event classification; Time from successful detect mode to classification complete. — 99 — ms Classification Time tCLASS Class 0/1/2/3 and Class 4 PoE; — 30 — ms Class 4 PoE+ — 69 — ms Power-Up Turn-On Delay tPWRUP Class 0/1/2/3 and Class 4 PoE; Time from when a valid detection is completed until VOUT power is applied — 76 — ms Class 4 PoE+; Time from when a valid detection is completed until VOUT power is applied — 112 — ms Midspan Detect Back- off Time tBOM 2.0 — — s Error Delay Time Ted Time from error to restart of detec- tion in auto-restart mode. 2.0 — — s Disconnect Delay tDC_DIS — 350 — ms Note: These typical specifications are based on an ambient operating temperature of 25 °C and VIN =+50 V. |
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