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AD7606BSTZ-4 Datasheet(PDF) 9 Page - Analog Devices |
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AD7606BSTZ-4 Datasheet(HTML) 9 Page - Analog Devices |
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9 / 36 page  AD7606/AD7606-6/AD7606-4 Rev. 0 | Page 9 of 36 Limit at TMIN, TMAX Parameter Min Typ Max Unit Description t27 Delay from RD falling edge to FRSTDATA low 19 ns VDRIVE = 3.3 V to 5.25V 24 ns VDRIVE = 2.3 V to 2.7V t28 Delay from 16th SCLK falling edge to FRSTDATA low 17 ns VDRIVE = 3.3 V to 5.25V 22 ns VDRIVE = 2.3 V to 2.7V t29 24 ns Delay from CS rising edge until FRSTDATA three-state enabled 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. 2 In oversampling mode, typical tCONV for the AD7606-6 and AD7606-4 can be calculated using ((N × tCONV) + ((N − 1) × 1 μs)). N is the oversampling ratio. For the AD7606-6, tCONV = 3 μs; and for the AD7606-4, tCONV = 2 μs. 3 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <10 LSB performance matching between channel sets. 4 A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins. Timing Diagrams tCYCLE t3 t5 t2 t4 t1 t7 tRESET tCONV CONVST A, CONVST B CONVST A, CONVST B BUSY CS RESET Figure 2. CONVST Timing—Reading After a Conversion tCYCLE t3 t5 t6 t2 t1 tCONV CONVST A, CONVST B CONVST A, CONVST B BUSY CS t7 tRESET RESET Figure 3. CONVST Timing—Reading During a Conversion DATA: DB[15:0] FRSTDATA CS RD INVALID V1 V2 V3 V7 V8 V4 t10 t8 t13 t24 t26 t27 t14 t11 t15 t9 t16 t17 t29 Figure 4. Parallel Mode, Separate CS and RD Pulses |
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