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AD80066KRSZRL Datasheet(PDF) 4 Page - Analog Devices |
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AD80066KRSZRL Datasheet(HTML) 4 Page - Analog Devices |
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4 / 20 page  AD80066 Rev. A | Page 4 of 20 Parameter Min Typ Max Unit POWER DISSIPATION 4-Channel Mode at 24 MHz 490 mW 1-Channel Mode at 12 MHz 300 mW 4-Channel Mode at 8 MHz, Slow Power Mode3 165 mW 1 The linear input signal range is up to 3 V p-p when the CCD reference level is clamped to 3 V by the AD80066 input clamp (see ). Figure 2 2 The PGA gain is approximately linear-in-dB but varies nonlinearly with register code (see the section for more information). Programmable Gain Amplifiers (PGA) 3 Measured with Bit D1 of the configuration register set high for 8 MHz, low power operation. 2V TYP RESET TRANSIENT AVDD = 5V 3V BIAS SET BY INPUT CLAMP 1.5V OR 3V p-p MAX INPUT SIGNAL RANGE GND Figure 2. Input Signal with the CCD Reference Level Clamped to 3 V DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS mode, fADCCLK = 24 MHz, fCDSCLK1 = fCDSCLK2 = 6 MHz, CL = 10 pF, unless otherwise noted. Table 2. Parameter Symbol Min Typ Max Unit LOGIC INPUTS High Level Input Voltage VIH 2.0 V Low Level Input Voltage VIL 0.8 V High Level Input Current IIH 10 μA Low Level Input Current IIL 10 μA Input Capacitance CIN 10 pF LOGIC OUTPUTS (DRVDD = 5 V) High Level Output Voltage (IOH = 2 mA) VOH 4.5 V Low Level Output Voltage (IOL = 2 mA) VOL 0.5 V LOGIC OUTPUTS (DRVDD = 3 V) High Level Output Voltage (IOH = 2 mA) VOH 2.5 V Low Level Output Voltage (IOL = 2 mA) VOL 0.5 V |
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