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ADIS16385 Datasheet(PDF) 9 Page - Analog Devices |
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ADIS16385 Datasheet(HTML) 9 Page - Analog Devices |
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9 / 20 page  Preliminary Technical Data ADIS16385 Rev. PrA | Page 9 of 20 BASIC OPERATION The ADIS16385 is an autonomous system that requires no user initialization. When it has a valid power supply, it initializes itself and starts sampling, processing, and loading sensor data into the output registers at a sample rate of 1024 SPS. DIO1 pulses high after each sample cycle concludes. The SPI interface enables simple integration with many embedded processor platforms, as shown in Figure 10 (electrical connection) and Table 6 (pin descriptions). SYSTEM PROCESSOR SPI MASTER ADIS16360/ ADIS16365 SPI SLAVE SCLK CS DIN DOUT SCLK SS MOSI MISO 5V IRQ DIO1 VDD I/O LINES ARE COMPATIBLE WITH 3.3V OR 5V LOGIC LEVELS 10 6 3 5 4 7 11 12 13 14 15 ADIS16385 Figure 10. Electrical Connection Diagram Table 6. Generic Master Processor Pin Names and Functions Pin Name Function SS Slave select SCLK Serial clock MOSI Master output, slave input MISO Master input, slave output IRQ Interrupt request The ADIS16385 SPI interface supports full duplex serial communication (simultaneous transmit and receive) and uses the bit sequence shown in Figure 14. Table 7 provides a list of the most common settings that require attention to initialize a processor’s serial port for the ADIS16385 SPI interface. Table 7. Generic Master Processor SPI Settings Processor Setting Description Master The ADIS16385 operates as a slave SCLK Rate ≤ 2 MHz1 Maximum serial clock rate SPI Mode 3 CPOL = 1 (polarity), CPHA = 1 (phase) MSB First Mode Bit sequence 16-Bit Mode Shift register/data length 1 For burst read, SCLK rate ≤ 1 MHz. For low power mode, SCLK rate ≤ 300 kHz. READING SENSOR DATA The ADIS16385 provides two different options for acquiring sensor data: single register and burst register. A single register read requires two 16-bit SPI cycles. The first cycle requests the contents of a register using the bit assignments in Figure 14. Bit DC7 to Bit DC0 are don’t care for a read, and then the output register contents follow on DOUT during the second sequence. Figure 11 includes three single register reads in succession. In this example, the process starts with DIN = 0x0400 to request the contents of XGYRO_OUT, and follows with 0x0600 to request YGYRO_OUT, and 0x0800 to request ZGYRO_OUT. Full duplex operation enables processors to use the same 16-bit SPI cycle to read data from DOUT while requesting the next set of data on DIN. Figure 12 provides an example of the four SPI signals when reading XGYRO_OUT in a repeating pattern. Figure 11. SPI Read Example Figure 12. Example SPI Read, Second 16-Bit Sequence Burst-Read Function The burst-read function enables the user to read all output registers using one command on the DIN line and shortens the stall time between each 16-bit segment to 1 SCLK cycle (see Table 2). Figure 13 provides the burst-read sequence of data on each SPI signal. The sequence starts with writing 0x3E00 to DIN, followed by each output register clocking out on DOUT, in the order in which they appear in Table 8. Figure 13. Burst-Read Sequence R/W R/W A6 A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 CS SCLK DIN DOUT A6 A5 D13 D14 D15 NOTES 1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0. Figure 14. SPI Communication Bit Sequence |
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