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SA56004DDP Datasheet(PDF) 8 Page - NXP Semiconductors

Part # SA56004DDP
Description  짹1 째C accurate, SMBus-compatible, 8-pin, remote/local digital temperature sensor with overtemperature alarms
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SA56004DDP Datasheet(HTML) 8 Page - NXP Semiconductors

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SA56004X_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 22 May 2008
8 of 36
NXP Semiconductors
SA56004X
Digital temperature sensor with overtemperature alarms
7.8 SA56004X SMBus registers
7.8.1 Command register
The command register selects which register will be read or written to. Data for this
register should be transmitted during the Command Byte of the SMBus write
communication.
7.8.2 Local and remote temperature registers (LTHB, LTLB, RTHB, RTLB)
7.8.3 Configuration register (CON)
The configuration register is an 8-bit register with read address 03h and write address
09h. Table 7 shows how the bits in this register are used.
Table 5.
Temperature data format
Temperature
Digital output
Binary
Hex
+125
°C
0111 1101 0000 0000
7D00h
+25
°C
0001 1001 0000 0000
1900h
+1
°C
0000 0001 0000 0000
0100h
+0.125
°C
0000 0000 0010 0000
0020h
0
°C
0000 0000 0000 0000
0000h
−0.125 °C
1111 1111 1110 0000
FFE0h
−1 °C
1111 1111 0000 0000
FF00h
−25 °C
1110 0111 0000 0000
E700h
−55 °C
1100 1001 0000 0000
C900h
Table 6.
LTHB, LTLB, RTHB, RTLB - Local and remote temperature registers
Byte
High byte (read only; address 00h, 01h)
Low byte (read only; address 10h)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Value
sign
64
32
16
8421
0.5
0.25
0.125
00000
Table 7.
CON - Configuration register (read address 03h; write address 09h)
bit assignments
Bit
Description
POR state
7
ALERT mask.
The ALERT interrupt is enabled when this bit is LOW. The ALERT interrupt
is disabled (masked) when this bit is HIGH.
0
6
RUN/STOP.
Standby or run mode control. Running mode is enabled when this bit is
LOW. The SA56004X is in standby mode when this bit is HIGH.
0
5
Not defined; defaults to logic 0.
0
4
Remote T_CRIT mask.
The T_CRIT output will be activated by a remote temperature that exceeds
the remote T_CRIT setpoint when this bit is LOW. The T_CRIT output will
not be activated under this condition when this bit is HIGH.
0
3
Not defined; defaults to logic 0.
0


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