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SC16IS750IBS Datasheet(HTML) 22 Page - NXP Semiconductors

Part No. SC16IS750IBS
Description  Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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SC16IS750IBS Datasheet(HTML) 22 Page - NXP Semiconductors

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[1]
These registers are accessible only when LCR[7] = 0.
[2]
These bits in can only be modified if register bit EFR[4] is enabled.
[3]
These bits are reserved and should be set to 0.
[4]
Only available on the SC16IS750/SC16IS760.
[5]
After Receive FIFO or Transmit FIFO reset (through FCR[1:0]), the user must wait at least 2
× T
clk of XTAL1 before reading or writing data to RHR and THR, respectively.
[6]
Burst reads on the serial interface (that is, reading multiple elements on the I2C-bus without a STOP or repeated START condition, or reading multiple elements on the SPI bus
without de-asserting the CS pin), should not be performed on the IIR register.
[7]
These registers are accessible only when MCR[2] = 1 and EFR[4] = 1.
[8]
IrDA mode slow/fast for SC16IS760, slow only for SC16IS750.
[9]
The special register set is accessible only when LCR[7] = 1 and not 0xBF.
[10] Enhanced Feature Registers are only accessible when LCR = 0xBF.
Special register set[9]
0x00
DLL
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
0x01
DLH
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
Enhanced register set[10]
0x02
EFR
Auto CTS
Auto RTS
special
character
detect
enable
enhanced
functions
software flow
control bit 3
software flow
control bit 2
software flow
control bit 1
software flow
control bit 0
R/W
0x04
XON1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
0x05
XON2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
0x06
XOFF1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
0x07
XOFF2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
Table 10.
SC16IS740/750/760 internal registers …continued
Register
address
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W


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