Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.NET

X  

Preview PDF Download HTML

SC16IS750IBS Datasheet(HTML) 33 Page - NXP Semiconductors

Part No. SC16IS750IBS
Description  Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
Download  62 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo 

SC16IS750IBS Datasheet(HTML) 33 Page - NXP Semiconductors

Zoom Inzoom in Zoom Outzoom out
Go To Page :
/ 62 page
background image
SC16IS740_750_760_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 13 May 2008
33 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.15 Receiver FIFO Level register (RXLVL)
This register is a read-only register, it reports the fill level of the receive FIFO. That is, the
number of characters in the RX FIFO.
8.16 Programmable I/O pins Direction register (IODir)
This register is only available on the SC16IS750 and SC16IS760. This register is used to
program the I/O pins direction. Bit 0 to bit 7 controls GPIO0 to GPIO7.
Remark: If there is a pending input (GPIO) interrupt and IODir is written, this pending
interrupt will be cleared, that is, the interrupt signal will be negated.
8.17 Programmable I/O pins State Register (IOState)
This register is only available on the SC16IS750 and SC16IS760. When ‘read’, this
register returns the actual state of all I/O pins. When ‘write’, each register bit will be
transferred to the corresponding IO pin programmed as output.
8.18 I/O Interrupt Enable Register (IOIntEna)
This register is only available on the SC16IS750 and SC16IS760. This register enables
the interrupt due to a change in the I/O configured as inputs. If GPIO[7:4] are programmed
as modem pins, their interrupt generation must be enabled via IER register bit 3. In this
case bit 7 to bit 4 of IOIntEna will have no effect on GPIO[7:4].
Table 26.
Receiver FIFO Level register bits description
Bit
Symbol
Description
7
-
not used; set to zeros
6:0
RXLVL[6:0]
number of characters stored in RX FIFO, from 0 (0x00) to 64 (0x40)
Table 27.
IODir register bits description
Bit
Symbol
Description
7:0
IODir
set GPIO pins [7:0] to input or output
0 = input
1 = output
Table 28.
IOState register bits description
Bit
Symbol
Description
7:0
IOState
Write this register:
set the logic level on the output pins
0 = set output pin to zero
1 = set output pin to one
Read this register:
return states of all pins
Table 29.
IOIntEna register bits description
Bit
Symbol
Description
7:0
IOIntEna
input interrupt enable
0 = a change in the input pin will not generate an interrupt
1 = a change in the input will generate an interrupt


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62 


Datasheet Download




Link URL



Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Bookmark   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn