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SC16IS750IBS Datasheet(HTML) 10 Page - NXP Semiconductors

Part No. SC16IS750IBS
Description  Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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SC16IS750IBS Datasheet(HTML) 10 Page - NXP Semiconductors

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SC16IS740_750_760_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 13 May 2008
10 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
7.2.1 Auto RTS
Figure 9 shows RTS functional timing. The receiver FIFO trigger levels used in auto RTS
are stored in the TCR or FCR. RTS is active if the RX FIFO level is below the halt trigger
level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is deasserted.
The sending device (for example, another UART) may send an additional character after
the trigger level is reached (assuming the sending UART has another character to send)
because it may not recognize the deassertion of RTS until it has begun sending the
additional character. RTS is automatically reasserted once the receiver FIFO reaches the
resume trigger level programmed via TCR[7:4]. This reassertion allows the sending
device to resume transmission.
Fig 8.
Autoflow control (auto RTS and auto CTS) example
RX
FIFO
FLOW
CONTROL
TX
FIFO
PARALLEL
TO SERIAL
TX
FIFO
RX
FIFO
UART 1
UART 2
RX
TX
RTS
CTS
TX
RX
CTS
RTS
002aab656
SERIAL TO
PARALLEL
SERIAL TO
PARALLEL
FLOW
CONTROL
FLOW
CONTROL
FLOW
CONTROL
PARALLEL
TO SERIAL
(1) N = receiver FIFO trigger level.
(2) The two blocks in dashed lines cover the case where an additional character is sent, as described in Section 7.2.1
Fig 9.
RTS functional timing
start
character
N
start
character
N + 1
start
stop
stop
RX
RTS
receive
FIFO
read
N
N + 1
12
002aab040


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