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I.MX27 Datasheet(PDF) 21 Page - Freescale Semiconductor, Inc |
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I.MX27 Datasheet(HTML) 21 Page - Freescale Semiconductor, Inc |
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21 / 148 page  i.MX27 and i.MX27L Data Sheet, Rev. 1.5 Freescale Semiconductor 21 Functional Description and Application Information 2.3.29 Run-TIme Integrity Checker (RTIC) The Run-Time Integrity Checker (RTIC) is one of the security components in the i.MX27/MX27L processors. Its purpose is to ensure the integrity of the peripheral memory contents and assist with boot authentication. The RTIC has the ability to verify the memory contents during system boot and during run-time execution. If the memory contents at runtime fail to match the hash signature, an error in the security monitor is triggered. Contact your Freescale Semiconductor sales office or distributor for additional information on SCC, RTIC, IIM, SAHARA2 2.3.30 Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2) SAHARA2 is a security co-processor, it implements encryption algorithms (AES, DES, and 3DES), hashing algorithms (MD5, SHA-1, SHA_224, and SHA-256), stream cipher algorithm (ARC4), and a hardware random number generator. Contact your Freescale Semiconductor sales office or distributor for additional information on SCC, RTIC, IIM, SAHARA2 2.3.31 Security Controller Module (SCC) The Security Controller Module (SCC) is a hardware security component. Overall, its primary functionality is associated with establishing a centralized security state controller and hardware security state with a hardware configured, unalterable security policy. Contact your Freescale Semiconductor sales office or distributor for additional information on SCC, RTIC, IIM, and SAHARA2. 2.3.32 Secure Digital Host Controller (SDHC) The Secure Digital Host Controller (SDHC) controls the MultiMedia Card (MMC), Secure Digital (SD) memory, and I/O cards by sending commands to cards and performing data accesses to/from the cards. The Multimedia Card/Secure Digital Host (MMC/SD) module integrates both MMC support along with SD memory and I/O functions. The SDHC is fully compatible with the MMC System Specification Version 3.0, as well as with the SD Memory Card Specification 1.0, and SD I/O Specification 1.0 with 1/4 channel(s). The maximum data rate in 4-bit mode is 100 Mbps. The SDHC uses a built-in programmable frequency counter for the SDHC bus, and provides a maskable hardware interrupt for an SDIO interrupt, internal status, and FIFO status. It has a pair of 32 × 16-bit data FIFO buffers built in. The MultiMedia Card (MMC) is a universal, low-cost data storage and communication media that is designed to cover a wide area of applications, including, for example, electronic toys, organizers, PDAs, and smart phones. The MMC communication is based on an advanced 7-pin serial bus designed to operate in a low-voltage range. The Secure Digital Card (SD) is an evolution of MMC technology, with two additional pins in the form factor. It is specifically designed to meet the security, capacity, performance, and environment requirements inherent in newly emerging audio and video consumer electronic devices. The physical form |
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Similar Description - I.MX27 |
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