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I.MX27 Datasheet(PDF) 77 Page - Freescale Semiconductor, Inc |
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I.MX27 Datasheet(HTML) 77 Page - Freescale Semiconductor, Inc |
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77 / 148 page  i.MX27 and i.MX27L Data Sheet, Rev. 1.5 Freescale Semiconductor 77 Electrical Characteristics NOTE SDR SDRAM CLK parameters are being measured from the 50% point—that is, high is defined as 50% of signal value and low is defined as 50% of signal value. The timing parameters are similar to the ones used in SDRAM data sheets—that is, Table 39 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. SD3 SDRAM clock cycle time tCK 7.5 — ns SD6 Address setup time tAS 1.8 — ns SD7 Address hold time tAH 1.8 — ns SD10 Precharge cycle period1 tRP 1 4 clock SD11 Auto precharge command period1 tRC 2 20 clock Note: 1 SD10 and SD11 are determined by SDRAM controller register settings. Table 39. SDRAM Refresh Timing Parameters (continued) ID Parameter Symbol Min Max Unit |
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