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LTC6990HS6-PBF Datasheet(PDF) 12 Page - Linear Technology |
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LTC6990HS6-PBF Datasheet(HTML) 12 Page - Linear Technology |
12 / 28 page LTC6990 12 6990p OPERATION On start-up, the DIV pin A/D converter must determine the correct DIVCODE before the output is enabled. If VDIV is not stable, it will increase the start-up time as the converter waits for a stable result. Therefore, capacitance on the DIV pin should be minimized so it will settle quickly. Less than 100pF will not affect performance. Output Enable The OE pin controls the state of the LTC6990’s output as seen on the OUT pin. Pulling the OE pin high enables the oscillator output. Pulling it low disables the output. When the output is disabled, it is either held low or placed in a high impedance state as dictated by the Hi-Z bit value (determined by the DIVCODE as described earlier). Table 2 summarizes the output control states. Table 2. Output States OE Pin Hi-Z OUT 1 X Enabled, Output is Active 0 1 Disabled, Output is Hi-Z 0 0 Disabled, Output is Held Low Figure 3 illustrates the timing for the OE function when Hi-Z = 0. When OE is low, the output is disabled and OUT is held low. Bringing OE high enables the output after a delay, tENABLE, which synchronizes the enable to eliminate sliver pulses and guarantee the correct width for the first pulse. If NDIV = 1 or 2 this delay will be no longer than the output period, tOUT. If NDIV > 2 the delay is limited to twice the internal master oscillator period (or 2 • tMASTER). Forcing OE low will bring OUT low after a propagation delay, tPD. If the output is high when OE falls, the output pulse will be truncated. As shown in Figure 4, setting Hi-Z = 1 places the output in a high-impedance state when OE = 0. This feature allows for “wired-OR” connections of multiple devices. Driving OE high enables the output. The output will usually be forced low during this time, although it is possible for OUT to transition directly from high-impedance to a high output, depending on the timing of the OE transition relative to the internal oscillator. Once high, the first output pulse will have the correct width (unless truncated by bringing OE low again). Figure 3. OE Timing Diagram (Hi-Z = 0) 6990 F03 OE OUT tPD tPD tENABLE tENABLE tOUT Figure 4. OE Timing Diagram (Hi-Z = 1) 6990 F04 OE OUT tPD tPD tPD tPD tENABLE tENABLE tOUT Hi-Z |
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