ADS62P15IRGCR datasheet(10/64 Pages) TI

Part #	ADS62P15IRGCR

Description	Dual Channel 11-Bits,125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs

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ADS62P15

SLAS572B – OCTOBER 2007 – REVISED APRIL 2009 .................................................................................................................................................... www.ti.com

TIMING REQUIREMENTS – LVDS AND CMOS MODES (continued)

Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD

= 3.3V, DRVDD = 1.8V to 3.3V, sampling frequency = 125MSPS, sine wave input clock, 3VPP clock amplitude, CLOAD = 5pF ,

Io = 3.5mA, RLOAD = 100Ω , no internal termination, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Fall time measured from 80% to 20% of DRVDD

tCLKFALL

Output clock fall time

0.7

1.5

2.5

ns

1 MSPS

≤ Sampling frequency ≤ 125 MSPS

PARALLEL CMOS INTERFACE, DRVDD = 1.8V, maximum buffer drive strength(8)

tSTART

Start time

Input clock rising edge to data getting valid, (9)(10)

8.5

ns

tDV

Width of valid data window

3.3

6.0

ns

PARALLEL CMOS INTERFACE, DRVDD = 1.8V, MULTIPLEXED MODE, FS = 65 MSPS, maximum buffer drive

strength

tSTART_CHA

Start time, channel A

Input clock falling edge to channel A data getting valid, (9) (10)

0.8

2.3

ns

tDV_CHA

Data valid, channel A

Width of valid data window

5.4

6.4

ns

tSTART_CHB

Start time, channel B

Input clock rising edge to channel B data getting valid

1.1

2.4

ns

tDV_CHB

Data valid, channel B

Width of valid data window

5

6

ns

PARALLEL CMOS INTERFACE, DRVDD = 1.8V, MULTIPLEXED MODE, FS = 40 MSPS, maximum buffer drive

strength

tSTART_CHA

Start time, channel A

Input clock falling edge to channel A data getting valid, (9) (10)

–4.5

–3

ns

tDV_CHA

Data valid, channel A

Width of valid data window

10.3

11.3

ns

tSTART_CHB

Start time, channel B

Input clock rising edge to channel B data getting valid

–4.1

–2.5

ns

tDV_CHB

Data valid, channel B

Width of valid data window

9.7

10.7

ns

(8)

For DRVDD < 2.2V, output clock cannot be used for data capture. A delayed version of the input clock can be used, that gives the

desired setup & hold times at the receiving chip

(9)

Data valid refers to LOGIC HIGH of 1.26V and LOGIC LOW of 0.54V for DRVDD = 1.8V.

(10) Measured from zero-crossing of input clock having 50% duty cycle.

Table 2. Timing Characteristics at Lower Sampling Frequencies

tsu DATA SETUP TIME, ns

th DATA HOLD TIME, ns

Sampling Frequency, MSPS

MIN

TYP

MAX

MIN

TYP

MAX

CMOS INTERFACE, DRVDD = 2.5 TO 3.3V

105

2.8

4.3

2.7

4.2

80

4.3

5.8

4.2

5.7

65

5.7

7.2

5.6

7.1

40

10.5

12

10.3

11.8

20

23

24.5

23

24.5

DDR LVDS INTERFACE, DRVDD = 3.3V

105

1

2.3

80

2.4

3.8

65

3.8

5.2

1.0

2.3

40

8.5

10

20

21

22.5

10

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