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SN74LV373AZQNR Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LV373AZQNR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 22 page SN54LV373A, SN74LV373A OCTAL TRANSPARENT DTYPE LATCHES WITH 3STATE OUTPUTS SCLS407J − APRIL 1998 − REVISED APRIL 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. terminal assignments 1234 A 1Q OE VCC 8Q B 2D 7D 1D 8D C 3Q 2Q 6Q 7Q D 4D 5D 3D 6D E GND 4Q LE 5Q FUNCTION TABLE (each latch) INPUTS OUTPUT OE LE D OUTPUT Q L H H H L HL L L LX Q0 H X X Z logic diagram (positive logic) OE To Seven Other Channels 1 11 3 2 LE 1D C1 1D 1Q Pin numbers shown are for the DB, DGV, DW, FK, J, NS, PW, RGY, and W packages. GQN PACKAGE (TOP VIEW) 1 234 A B C D E |
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