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BQ78PL114RGZT Datasheet(PDF) 8 Page - Texas Instruments |
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BQ78PL114RGZT Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 31 page  bq78PL114 SLUS850B – SEPTEMBER 2008 – REVISED APRIL 2009................................................................................................................................................ www.ti.com bq78PL114 TERMINAL FUNCTIONS (continued) NAME NO. TYPE(1) DESCRIPTION EFCID 5 I External discharge MOSFET control input LED1 32 O LED1 – open-drain, active-low LED2 33 O LED2 – open-drain, active-low LED3 34 O LED3 – open-drain, active-low LED4 35 O LED4 – open-drain, active-low LED5 36 O LED5 – open-drain, active-low LEDEN 31 IO LEDEN – common-anode drive (active-low) and pushbutton input NC 26 IO Connect 1-M Ω resistor to VSS NC 27 I Connect 1-M Ω resistor to VSS NC 28, 29 O No connect OSCI 11 I External oscillator input (no connect, internal oscillator used) OSCO 12 O External oscillator output (no connect, internal oscillator used) P1N 15 O Charge-balance gate drive, cell 1 north P2S 16 O Charge-balance gate drive, cell 2 south P2N 17 O Charge-balance gate drive, cell 2 north P3N 21 O Charge-balance gate drive, cell 3 north P3S 20 O Charge-balance gate drive, cell 3 south P4N 23 O Charge-balance gate drive, cell 4 north P4S 22 O Charge-balance gate drive, cell 4 south P-LAN 24 IO PowerLAN I/O to external bq76PL102 nodes PRE 3 O Precharge MOSFET control (active-high) RSTN 25 I Device reset, active-low SDI1 14 I Connect to SDO0 via a capacitor SDI3 19 I Internal PowerLAN connection – connect to SDO2 through a 0.01- µF capacitor SDO0 13 O Requires 100-k Ω pullup resistor to VLDO1 SDO2 18 O Internal PowerLAN connection – connect to SDI3 through a 0.01- µF capacitor SMBCLK 37 IO SMBus clock signal SMBDAT 38 IO SMBus data signal SPROT 30 O Secondary protection output, active-high (FUSE) V1 47 IA Cell-1 positive input V2 44 IA Cell-2 positive input V3 42 IA Cell-3 positive input V4 39 IA Cell-4 positive input VLDO1 8 P Internal LDO-1 output, bypass with 10- µF capacitor to VSS VLDO2 43 P Internal LDO-2 output, bypass with 10- µF capacitor to V2 VSS 48 IA Cell-1 negative input XT1 46 IA External temperature-sensor-1 input XT2 45 IA External temperature-sensor-2 input XT3 41 IA External temperature-sensor-3 input XT4 40 IA External temperature-sensor-4 input – – P Thermal pad. Connect to VSS 8 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq78PL114 |
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