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74CB3Q3384ADBQRG4 Datasheet(PDF) 2 Page - Texas Instruments |
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74CB3Q3384ADBQRG4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 15 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) 1A1 SW 1B1 1A5 1OE SW 1B5 2A1 SW 2B1 2A5 2OE SW 2B5 3 11 1 14 22 13 2 10 15 23 SN74CB3Q3384A 10-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH SCDS114D – DECEMBER 2002 – REVISED JUNE 2005 The SN74CB3Q3384A is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3384A provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems. The SN74CB3Q3384A is organized as two 5-bit bus switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 5-bit bus switches or as one 10-bit bus switch. When OE is low, the associated 5-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 5-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (EACH 5-BIT BUS SWITCH) INPUT INPUT/OUTPUT FUNCTION OE A L B A port = B port H Z Disconnect LOGIC DIAGRAM (POSITIVE LOGIC) 2 |
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