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SN74LVC374ADWR Datasheet(PDF) 1 Page - Texas Instruments |
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SN74LVC374ADWR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 26 page www.ti.com FEATURES 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK SN54LVC374A . . . J OR W PACKAGE SN74LVC374A . . . DB, DGV, DW, N, NS, OR PW PACKAGE (TOP VIEW) SN54LVC374A . . . FK PACKAGE (TOP VIEW) 3 2 1 20 19 9 10 11 12 13 4 5 6 7 8 18 17 16 15 14 8D 7D 7Q 6Q 6D SN74LVC374A . . . RGY PACKAGE (TOP VIEW) 1 20 10 11 2 3 4 5 6 7 8 9 19 18 17 16 15 14 13 12 8Q 8D 7D 7Q 6Q 6D 5D 5Q 1Q 1D 2D 2Q 3Q 3D 4D 4Q 2D 2Q 3Q 3D 4D DESCRIPTION/ORDERING INFORMATION SN54LVC374A, SN74LVC374A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS296N – JANUARY 1993 – REVISED MAY 2005 • Ioff Supports Partial-Power-Down Mode Operation • Operate From 1.65 V to 3.6 V • Latch-Up Performance Exceeds 250 mA Per • Inputs Accept Voltages to 5.5 V JESD 17 • Max tpd of 6.5 ns at 3.3 V • ESD Protection Exceeds JESD 22 • Typical VOLP (Output Ground Bounce) – 2000-V Human-Body Model (A114-A) <0.8 V at VCC = 3.3 V, TA = 25°C – 200-V Machine Model (A115-A) • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C – 1000-V Charged-Device Model (C101) • Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) The SN54LVC374A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC374A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 1993–2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas On products compliant to MIL-PRF-38535, all parameters are Instruments standard warranty. Production processing does not tested unless otherwise noted. On all other products, production necessarily include testing of all parameters. processing does not necessarily include testing of all parameters. |
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