1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

GND

SDI

CLK

LE(ED1)

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

VDD

R-EXT

SDO

OE(ED2)

OUT15

OUT14

OUT13

OUT12

OUT11

OUT10

OUT9

OUT8

DBQ, DW, OR PWP PACKAGE

(TOP VIEW)

TLC5926, TLC5927

Pin Descriptions

PIN NAME

DESCRIPTION

CLK

Clock input pin for data shift on rising edge

GND

Ground pin for control logic and current sink

Data strobe input pn

Serial data is transferred to the respective latch when LE(ED1) is high. The data is latched when LE(ED1) goes low.

LE(ED1)

Also, a control signal input for an Error Detection mode and Current Adjust mode (See Timing Diagram). LE(ED1) has

an internal pulldown.

Output enable pin. When OE (ED2)(active) is low, the output drivers are enabled; when OE(ED2) is high, all output

OE(ED2)

drivers are turned OFF (blanked). Also, a control signal input for an Error Detection mode and Current Adjust mode

(See Timing Diagram). OE(ED2) has an internal pull-up.

OUT0–OUT15

Constant-current output pins

R-EXT

Input pin used to connect an external resistor for setting up all output currents

SDI

Serial-data input to the Shift register

SDO

Serial-data output to the following SDI of next driver IC or to the microcontroller

VDD

Supply voltage pin

Diagnostic Features

OPEN-LOAD

SHORT TO GND

DETECTION

DETECTION

DETECTION

TLC5926

x

x

TLC5927

x

x

x

(1)

The device has one single error register for all these conditions (one error bit per channel)

Copyright © 2008, Texas Instruments Incorporated

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Product Folder Link(s): TLC5926 TLC5927