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ADS1675 Datasheet(PDF) 6 Page - Texas Instruments |
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ADS1675 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 36 page ADS1675 SBAS416C – DECEMBER 2008 – REVISED SEPTEMBER 2009 ..................................................................................................................................... www.ti.com TERMINAL FUNCTIONS (continued) PIN NAME NO. FUNCTION DESCRIPTION Configure Low-Latency digital filter.(1) LL_CONFIG 32 Digital input If LL_CONFIG = '0', then single-cycle settling is selected. If LL_CONFIG = '1', then fast-response is selected. Digital filter path selection. FPATH 33 Digital input If FPATH = '0', then path is Wide-Bandwidth. If FPATH = '1', then path is Low-Latency. DRATE[2:0] 34-36 Digital input Data rate selection START 37 Digital input Start convert, reset, and synchronization control input CS 38 Digital input Chip select; active low OTRD 39 Digital output Digital filter out-of-range indicator OTRA 40 Digital input Analog input out-of-range indicator Negative shift clock output. SCLK 41 Digital output If SCLK_SEL = '0', then SCLK is the complementary shift clock output. If SCLK_SEL = '1', then SCLK always output is 3-state. Positive shift clock output. SCLK 42 Digital input/output If SCLK_SEL = '0', then SCLK is an output. If SCLK_SEL = '1', then SCLK is an input. DOUT 43 Digital output Negative LVDS serial data output DOUT 44 Digital output Positive LVDS serial data output DRDY 45 Digital output Negative data ready output DRDY 46 Digital output Positive data ready output CLK 55 Digital input Master clock input CAP1 59 Analog Terminal for 1 μF external bypass capacitor VREFN 60, 61 Analog Negative reference voltage. Short to analog ground CAP2 62 Analog Terminal for 1 μF external bypass capacitor VREFP 63, 64 Analog Positive reference voltage 6 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1675 |
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