ADP3212A, NCP3218A

http://onsemi.com

4

PIN ASSIGNMENT

Pin No.

Description

Mnemonic

11

TTSNS

Thermal Throttling Sense and Crowbar Disable Input. A resistor divider where the upper resistor is connected

to VCC, the lower resistor (NTC thermistor) is connected to GND, and the center point is connected to this

pin and acts as a temperature sensor half bridge. Connecting TTSNS to GND disables the thermal throttling

function and disables the crowbar, or Overvoltage Protection (OVP), feature of the chip.

12

GND

Analog and Digital Signal Ground.

13

IREF

This pin sets the internal bias currents. A 80 kW resistor is connected from this pin to ground.

14

RPM

RPM Mode Timing Control Input. A resistor between this pin to ground sets the RPM mode turn−on

threshold voltage.

15

RT

Multi−phase Frequency Setting Input. An external resistor connected between this pin and GND sets the

oscillator frequency of the device when operating in multi−phase PWM mode threshold of the converter.

16

RAMP

PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this pin sets

the slope of the internal PWM stabilizing ramp used for phase−current balancing.

17

LLINE

Output Load Line Programming Input. The center point of a resistor divider between CSREF and

CSCOMP is connected to this pin to set the load line slope.

18

CSREF

Current Sense Reference Input. This pin must be connected to the common point of the output inductors.

The node is shorted to GND through an internal switch when the chip is disabled to provide soft stop

transient control of the converter output voltage.

19

CSSUM

Current Sense Summing Input. External resistors from each switch node to this pin sum the inductor

currents to provide total current information.

20

CSCOMP

Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the gain of

the current−sense amplifier and the positioning loop response time.

21

ILIM

Current Limit Setpoint. An external resistor from this pin to CSCOMP sets the current limit threshold of the

converter.

22

OD3

Multi−phase Output Disable Logic Output. This pin is actively pulled low when the APD3212A/NCP3218A

enters single−phase mode or during shutdown. Connect this pin to the SD inputs of the Phase−3 MOSFET

drivers.

23

PWM3

Logic−Level PWM Output for phase 3. Connect to the input of an external MOSFET driver such as the

ADP3611.

24

SWFB3

Current Balance Input for phase 3. Input for measuring the current level in phase 3. SWFB3 should be left

open for 1 or 2 phase configuration.

25

BST2

High−Side Bootstrap Supply for Phase 2. A capacitor from this pin to SW2 holds the bootstrapped voltage

while the high−side MOSFET is on.

26

DRVH2

High−Side Gate Drive Output for Phase 2.

27

SW2

Current Return for High−Side Gate Drive for phase 2.

28

SWFB2

Current Balance Input for phase 2. Input for measuring the current level in phase 2. SWFB2 should be left

open for 1 phase configuration.

29

DRVL2

Low−Side Gate Drive Output for Phase 2.

30

PGND

Low−Side Driver Power Ground

31

DRVL1

Low−Side Gate Drive Output for Phase 1.

32

PVCC

Power Supply Input/Output of Low−Side Gate Drivers.

33

SWFB1

Current Balance Input for phase 1. Input for measuring the current level in phase 1.

34

SW1

Current Return For High−Side Gate Drive for phase 1.

35

DRVH1

High−Side Gate Drive Output for Phase 1.

36

BST1

High−Side Bootstrap Supply for Phase 1. A capacitor from this pin to SW1 holds the bootstrapped voltage

while the high−side MOSFET is on.

37

VCC

Power Supply Input/Output of the Controller.

38

PH1

Phase Number Configuration Input. Connect to VCC for 3 phase configuration.

39

PH0

Phase Number Configuration Input. Connect to GND for 1 phase configuration. Connect to VCC for

multi−phase configuration.

40

DPRSLP

Deeper Sleep Control Input.

41

PSI

Power State Indicator Input. Pulling this pin to GND forces the APD3212A/NCP3218A to operate in

single−phase mode.

42 to

48

VID6 to VID0

Voltage Identification DAC Inputs. When in normal operation mode, the DAC output programs the FB

regulation voltage from 0.3 V to 1.5 V (see Table 3).