ADP3212A, NCP3218A

http://onsemi.com

3

ABSOLUTE MAXIMUM RATINGS

Parameter

Rating

Unit

−0.3 to +6.0

V

FBRTN, PGND1, PGND2

−0.3 to +0.3

V

BST1, BST2, DRVH1, DRVH2

DC

t < 200 ns

−0.3 to +28

−0.3 to +33

V

DC

t < 200 ns

−0.3 to +22

−0.3 to +28

V

BST1 to SW1, BST2 to SW2

−0.3 to +6.0

V

SW1, SW2

DC

t < 200 ns

−1.0 to +22

−6.0 to +28

V

DRVH1 to SW1, DRVH2 to SW2

−0.3 to +6.0

V

DRVL1 to PGND1, DRVL2 to PGND2

DC

t < 200 ns

−0.3 to +6.0

−5.0 to +6.0

V

RAMP (in Shutdown)

−0.3 to +22

V

All Other Inputs and Outputs

−0.3 to +6.0

V

Storage Temperature Range

−65 to +150

°C

Operating Ambient Temperature Range

−40 to +100

°C

Operating Junction Temperature

125

°C

30.5

°C/W

Lead Temperature

Soldering (10 sec)

Infrared (15 sec)

300

260

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.

PIN ASSIGNMENT

Pin No.

Mnemonic

Description

1

EN

Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, pulls PWRGD and

VRTT low, and pulls CLKEN high.

2

PWRGD

Power−Good Output. Open−drain output. A low logic state means that the output voltage is outside of the

VID DAC defined range.

3

IMON

Current Monitor Output. This pin sources a current proportional to the output load current. A resistor to

FBRTN sets the current monitor gain.

4

CLKEN

Clock Enable Output. Open−drain output. A low logic state enables the CPU internal PLL clock to lock to

the external clock.

5

FBRTN

Feedback Return Input/Output. This pin remotely senses the CPU core voltage. It is also used as the

ground return for the VID DAC and the voltage error amplifier blocks.

6

FB

Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.

7

COMP

Voltage Error Amplifier Output and Frequency Compensation Point.

8

TRDET

Transient Detect Output. This pin is pulled low when a load release transient is detected. During repetitive

load transients at high frequencies, this circuit optimally positions the maximum and minimum output

voltage into a specified loadline window.

9

VARFREQ

Variable Frequency Enable Input. A high logic state enables the PWM clock frequency to vary with VID code.

10

VRTT

Voltage Regulator Thermal Throttling Output. Logic high state indicates that the voltage regulator

temperature at the remote sensing point exceeded a set alarm threshold level.