ADP4000JCPZ-RL7 datasheet(11/37 Pages) ONSEMI

Part #	ADP4000JCPZ-RL7

Description	Programmable Multi-Phase Synchronous Buck Converter with PMBus

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ADP4000

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Description

The ADP4000 is a 6--Phase VR11.1 regulator with a

PMBus Interface Typical application circuits is shown in

Figure 2.

Startup Sequence

The ADP4000 follows the VR11 start-up sequence shown

in Figure 7. After both the EN and UVLO conditions are

met, a programmable internal timer goes through one delay

cycle TD1. This delay cycle is programmed using Delay

Command, default delay = 2 ms, see Table 1 for

programmable values). The first six clock cycles of TD2 are

blanked from the PWM outputs and used for phase detection

as explained in the following section. Then the

programmable internal soft--start ramp is enabled (TD2) and

the output comes up to the boot voltage of 1.1V. The boot

hold time is also set by Delay Command. This second delay

cycle is called TD3. During TD3 the processor VID pins

settle to the required VID code. When TD3 is over, the

ADP4000 reads the VID inputs and soft--starts either up or

down to the final VID voltage (TD4). After TD4 has been

completed and the PWRGD masking time (equal to VID on

the fly masking) is finished, a third cycle of the internal timer

sets the PWRGD blanking (TD5).

The internal delay and soft--start times are programmable

using the serial interface and the Delay Command and the

Soft--Start Commands.

Figure 7. System Startup Sequence for VR11

TD1

TD3

TD2

TD5

50 ms

TD4

5.0 V

SUPPLY

VTT I/O

(ADP4000 EN)

VCC_CORE

VR READY

(ADP4000 PWRGD)

CPU

VID INPUTS

VID INVALID

VID VALID

VBOOT

(1.1 V)

UVLO

THRESHOLD

0.85 V

VVID

Internal Delay Timer

An internal timer sets the delay times for the startup

sequence, TD1, TD3 and TD5. The default time is 2msec,

which can be changed using the PMBus interface. This timer

is used for multiple delay timings (TD1, TD3 and TD5)

during the startup sequence. Also, it is used for timing the

current--limit latchoff as explained in the Current--Limit

section. The current--limit timer is set to 4 times the delay

timer.

Table 1. Delay Codes

Code

Delay (msec)

000

0.5

001

1

010

1.5

011

2 = default

100

2.5

101

3

110

3.5

111

4

The delay timer is programmed using Bits <2:0> of the

Ton Delay command (0xD4). The delay can be programmed

between 0.5 msec and 4 msec. Table 1 provides the

programmable delay times.

Soft--Start

The soft--start slope for the output voltage is set by an

internal timer. The default value is 0.5 V/msec, which can be

programmed through the PMBus interface. After TD1 and

the phase detection cycle have been completed, the SS time

(TD2 in Figure 7) starts. The SS circuit uses the internal VID

DAC to increase the output voltage in 6.25 mV steps up to

the 1.1 V boot voltage.

Once the SS circuit has reached the boot voltage, the boot

voltage delay time (TD3) is started. The end of the boot

voltage delay time signals the beginning of the second

soft--start time (TD4). The SS voltage changes from the boot

voltage to the programmed VID DAC voltage (either higher

or lower) using 6.25 mV steps.

The soft--start slew rate is programmed using Bits <2:0>

of the Ton_Rise (0xD5) command code. Table 2 provides

the soft--start values

Table 2. Slew Rate Codes

Code

Slew Rate (V/msec)

000

0.1

001

0.3

010

0.5 = default

011

0.7

100

0.9

101

1.1

110

1.3

111

1.5

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ADP4000JCPZ-RL7 Datasheet(PDF) 11 Page - ON Semiconductor

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