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TDA19978A Datasheet(HTML) 12 Page - NXP Semiconductors

Part No. TDA19978A
Description  Quad HDMI 1.3a receiver interface with equalizer (HDTV up to 1080p, up to UXGA for PC formats)
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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TDA19978A Datasheet(HTML) 12 Page - NXP Semiconductors

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TDA19978A_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 16 April 2010
12 of 38
NXP Semiconductors
TDA19978A
Quad HDMI 1.3a receiver with digital processing
[1]
Can be activated with the I2C-bus (optional).
[1]
Can be activated with the I2C-bus (optional).
[1]
Can be activated with the I2C-bus (optional).
[2]
x in SDx and S/PDIFx relates to the actual frame.
Table 4.
Audio port configuration (Layout 0)
Audio port
Pin
Layout 0
I2S-bus
S/PDIF
OBA
AP5
85
SYSCLK[1]
SYSCLK[1]
AP4
83
WS (word select)
WS[1]
AP3
82
AP2
81
AP1
80
DSD channel 1
AP0
79
SD
S/PDIF
DSD channel 0
ACLK
78
SCK (I2S-bus clock)
64
× f
s
32
× f
s
master clock for S/PDIF[1]
64
× f
s
DSD clock
64
× f
s
Table 5.
Audio port configuration (Layout 1)
Audio port
Pin
Layout 1
I2S-bus
S/PDIF
OBA
AP5
85
SYSCLK[1]
SYSCLK[1]
DSD channel 5
AP4
83
WS (word select)
WS[1]
DSD channel 4
AP3
82
SD3
S/PDIF3
DSD channel 3
AP2
81
SD2
S/PDIF2
DSD channel 2
AP1
80
SD1
S/PDIF1
DSD channel 1
AP0
79
SD0
S/PDIF0
DSD channel 0
ACLK
78
SCK (I2S-bus clock)
64
× f
s
32
× f
s
master clock for S/PDIF[1]
64
× f
s
DSD clock
64
× f
s
Table 6.
Audio port configuration for HBR and DST packets
Audio port
Pin
HBR demultiplexed
DST
I2S-bus
S/PDIF
AP5
85
SYSCLK[1]
SYSCLK[1]
AP4
83
WS (word select)
WS[1]
frame_start
AP3
82
SDx+3
S/PDIFx+3
AP2
81
SDx+2
S/PDIFx+2
AP1
80
SDx+1
S/PDIFx+1
AP0
79
SDx
S/PDIFx
DSD channel 0
ACLK
78
SCK (I2S-bus clock)
64
× f
s (ACR)
32
× f
s (ACR)
master clock for S/PDIF[1]
64
× f
s
DSD clock
64
× f
s
128
× f
s


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