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CAT28C65BWA-90T Datasheet(PDF) 8 Page - ON Semiconductor |
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CAT28C65BWA-90T Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 13 page CAT28C65B 8 Doc. No. MD-1009, Rev. H © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice ADDRESS CE OE WE DATA OUT tAS DATA IN DATA VALID HIGH-Z tAH tWC tOEH tDH tDS tOES tBLC tCH tCS tCW RDY/BUSY tRB HIGH-Z HIGH-Z falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 5 ms. Page Write The page write mode of the CAT28C65B (essentially an extended BYTE WRITE mode) allows from 1 to 32 bytes of data to be programmed within a single EEPROM write cycle. This effectively reduces the byte-write time by a factor of 32. Following an initial WRITE operation ( WE pulsed low, for tWP, and then high) the page write mode can begin by issuing sequential WE pulses, which load the address and data bytes into a 32 byte temporary buffer. The page address where data is to be written, specified by bits A5 to A12, is latched on the last falling edge of WE. Each byte within the page is defined by address bits A0 to A4 Figure 5. Byte Write Cycle [CE Controlled] Figure 6. Page Mode Write Cycle OE CE WE ADDRESS I/O tWP tBLC BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2 LAST BYTE tWC |
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