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CAT34C02YI-GT5 Datasheet(PDF) 5 Page - ON Semiconductor

Part # CAT34C02YI-GT5
Description  2 kb I2C EEPROM for DDR2 DIMM Serial Presence Detect
Download  15 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CAT34C02YI-GT5 Datasheet(HTML) 5 Page - ON Semiconductor

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CAT34C02
http://onsemi.com
5
10
1
0
DEVICE ADDRESS
Figure 3. Slave Address Bits
A0
A1
A2
R/W
18
9
START
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
BUS RELEASE DELAY
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
Figure 4. Acknowledge Timing
(RECEIVER)
ACK SETUP (≥ tSU:DAT)
ACK DELAY (≤ tAA)
SCL
SDA IN
SDA OUT
Figure 5. Bus Timing
tSU:STO
tBUF
tSU:DAT
tSU:STA
tHD:STA
tHD:DAT
tAA
tF
tDH
tR
tLOW
tLOW
tHIGH
Write Operations
Byte Write
In Byte Write mode the Master sends a START, followed
by Slave address, byte address and data to be written
(Figure 6). The Slave acknowledges all 3 bytes, and the
Master then follows up with a STOP, which in turn starts the
internal Write operation (Figure 7). During internal Write,
the Slave will not acknowledge any Read or Write request
from the Master.
Page Write
The CAT34C02 contains 256 bytes of data, arranged in 16
pages of 16 bytes each. A page is selected by the 4 most
significant bits of the address byte following the Slave
address, while the 4 least significant bits point to the byte
within the page. Up to 16 bytes can be written in one Write
cycle (Figure 8).
The internal byte address counter is automatically
incremented after each data byte is loaded. If the Master
transmits more than 16 data bytes, then earlier bytes will be
overwritten by later bytes in a ‘wrap−around’ fashion
(within the selected page). The internal Write cycle starts
immediately following the STOP.
Acknowledge Polling
Acknowledge polling can be used to determine if the
CAT34C02 is busy writing or is ready to accept commands.
Polling is implemented by interrogating the device with a
‘Selective Read’ command (see READ OPERATIONS).
The CAT34C02 will not acknowledge the Slave address,
as long as internal Write is in progress.
Delivery State
The CAT34C02 is shipped ‘unprotected’, i.e. neither SWP
flag is set. The entire 2 kb memory is erased, i.e. all bytes are
FFh.


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