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CAT28F001LI-90TT Datasheet(PDF) 1 Page - ON Semiconductor |
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CAT28F001LI-90TT Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 18 page 1 Doc. No. MD-1078, Rev. K © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice 1 Megabit CMOS Boot Block Flash Memory FEATURES s Fast Read Access Time: 90/120 ns s On-Chip Address and Data Latches s Blocked Architecture — One 8 KB Boot Block w/ Lock Out • Top or Bottom Locations — Two 4 KB Parameter Blocks — One 112 KB Main Block s Low Power CMOS Operation s 12.0V ± 5% Programming and Erase Voltage s Automated Program & Erase Algorithms s High Speed Programming s Commercial, Industrial and Automotive Temperature Ranges s Deep Powerdown Mode — 0.05 µA I CC Typical — 0.8 µA I PP Typical s Hardware Data Protection s Electronic Signature s 100,000 Program/Erase Cycles and 10 Year Data Retention s JEDEC Standard Pinouts: — 32 pin DIP — 32 pin PLCC — 32 pin TSOP s Reset/Deep Power Down Mode s "Green" Package Options Available I/O0–I/O7 I/O BUFFERS CE, OE LOGIC SENSE AMP DATA LATCH ERASE VOLTAGE SWITCH COMMAND REGISTER CE OE WE VOLTAGE VERIFY SWITCH Y-DECODER X-DECODER Y-GATING 8K-BYTE BOOT BLOCK 4K-BYTE PARAMETER BLOCK 4K-BYTE PARAMETER BLOCK 112K-BYTE MAIN BLOCK A0–A16 WRITE STATE MACHINE ADDRESS COUNTER STATUS REGISTER PROGRAM VOLTAGE SWITCH RP BLOCK DIAGRAM DESCRIPTION The CAT28F001 is a high speed 128K X 8 bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after sale code updates. The CAT28F001 has a blocked architecture with one 8 KB Boot Block, two 4 KB Parameter Blocks and one 112 KB Main Block. The Boot Block section can be at the top or bottom of the memory map and includes a reprogram- ming write lock out feature to guarantee data integrity. It is designed to contain secure code which will bring up the system minimally and download code to other loca- tions of CAT28F001. The CAT28F001 is designed with a signature mode which allows the user to identify the IC manufacturer and device type. The CAT28F001 is also designed with on- Chip Address Latches, Data Latches, Programming and Erase Algorithms. The CAT28F001 is manufactured using Catalyst’s ad- vanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 32-pin plastic DIP, PLCC or TSOP packages. Licensed Intel second source CAT28F001 |
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