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CAT25128LI-T3 Datasheet(PDF) 9 Page - ON Semiconductor |
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CAT25128LI-T3 Datasheet(HTML) 9 Page - ON Semiconductor |
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9 / 16 page  CAT25128 http://onsemi.com 9 READ OPERATIONS Read from Memory Array To read from memory, the host sends a READ instruction followed by a 16−bit address (see Table 11 for the number of significant address bits). After receiving the last address bit, the CAT25128 will respond by shifting out data on the SO pin (as shown in Figure 9). Sequentially stored data can be read out by simply continuing to run the clock. The internal address pointer is automatically incremented to the next higher address as data is shifted out. After reaching the highest memory address, the address counter “rolls over” to the lowest memory address, and the read cycle can be continued indefinitely. The read operation is terminated by taking CS high. Read Status Register To read the status register, the host simply sends a RDSR command. After receiving the last bit of the command, the CAT25128 will shift out the contents of the status register on the SO pin (Figure 10). The status register may be read at any time, including during an internal write cycle. While the internal write cycle is in progress, the RDSR command will output the RDY (Ready) bit status only (i.e., data out = FFh). Figure 9. READ Timing SCK SI SO BYTE ADDRESS* 01 23 45 67 89 7 6 5 4 3 2 1 0 DATA OUT MSB HIGH IMPEDANCE OPCODE 21 20 22 23 24 25 26 27 28 29 30 00 00 0 1 1 Dashed Line = mode (1, 1) A0 AN CS * Please check the Byte Address Table (Table 11) 0 10 Figure 10. RDSR Timing 01 2 3 4 5 6 7 8 10 911 12 13 14 SCK SI DATA OUT MSB HIGH IMPEDANCE OPCODE SO 7 6 5 4 3 2 1 0 00 0 00 1 0 1 Dashed Line = mode (1, 1) CS |
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