CM1224

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Application Information

Design Considerations

To realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize

parasitic series inductances on the Supply/ Ground rails as well as the signal trace segment between the signal

input (typically a connector) and the ESD protection device. Application of Positive ESD Pulse between Input

Channel and Ground illustrates an example of a positive ESD pulse striking an input channel. The parasitic

series inductance back to the power supply is represented by L

voltage V

protected is:

V

CL

=

Fwd

voltage

drop

of

D

1

+

V

SUPPLY

+

L

1

x

d(I

/

dt

+ L

where I

An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact

discharge per the IEC61000-4-2 standard results in a current pulse that rises from 0 to 30 Amps in 1ns. Here

d(I

will lead to a 300V increment in V

Similarly for negative ESD pulses, parasitic series inductance from the V

drastically increased negative voltage on the line being protected.

The CM1224 has an integrated Zener diode between V

inductance L

possible V

recommended that a 0.22µF ceramic chip capacitor be connected between V

As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of

expected electrostatic discharges. The power supply bypass capacitor mentioned earlier should be as close to

the V

planes and between the signal input and the ESD device to minimize stray series inductance.

Additional Information

See also California Micro Devices Application Note AP209, “Design Considerations for ESD Protection,” in the

Applications section at www.calmicro.com.

Figure 3. Application of Positive ESD Pulse between Input Channel and Ground