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CM2030 Datasheet(PDF) 3 Page - ON Semiconductor |
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CM2030 Datasheet(HTML) 3 Page - ON Semiconductor |
3 / 17 page CM2030 Rev. 5 | Page 3 of 17 | www.onsemi.com PIN DESCRIPTIONS PINS NAME ESD Level DESCRIPTION 4, 35 TMDS_D2+ 8kV 3 TMDS 0.9pF ESD protection. 1 6, 33 TMDS_D2– 8kV 3 TMDS 0.9pF ESD protection. 1 7, 32 TMDS_D1+ 8kV 3 TMDS 0.9pF ESD protection. 1 9, 30 TMDS_D1– 8kV 3 TMDS 0.9pF ESD protection. 1 10, 29 TMDS_D0+ 8kV 3 TMDS 0.9pF ESD protection. 1 12, 27 TMDS_D0– 8kV 3 TMDS 0.9pF ESD protection. 1 13, 26 TMDS_CK+ 8kV 3 TMDS 0.9pF ESD protection. 1 15, 24 TMDS_CK– 8kV 3 TMDS 0.9pF ESD protection. 1 16 CE_REMOTE_IN 2kV 4 CE_SUPPLY referenced logic level in. 23 CE_REMOTE_OUT 8kV 3 5V_SUPPLY referenced logic level out plus 10pF ESD. 6 17 DDC_CLK_IN 2kV 4 LV_SUPPLY referenced logic level in. 22 DDC_CLK_OUT 8kV 3 5V_SUPPLY referenced logic level out plus 10pF ESD. 6 18 DDC_DAT_IN 2kV 4 LV_SUPPLY referenced logic level in. 21 DDC_DAT_OUT 8kV 3 5V_SUPPLY referenced logic level out plus 10pF ESD. 6 19 HOTPLUG_DET_IN 2kV 4 LV_SUPPLY referenced logic level in. 20 HOTPLUG_DET_OUT 8kV 3 5V_SUPPLY referenced logic level out plus 10pF ESD. A 0.1µF bypass ceramic capacitor is recommended on this pin. 2 2 LV_SUPPLY 2kV 4 Bias for CE / DDC / HOTPLUG level shifters. 37 CE_SUPPLY 2kV 4,2 CEC bias voltage. Previously CM2020 ESD_BYP pin. 1 5V_SUPPLY 2kV 4 Current source for 5V_OUT, VREF for DDC I 2C voltage references, and bias for 8kV ESD pins. 38 5V_OUT 8kV 3 55mA minimum overcurrent protected 5V output. This output must be bypassed with a 0.1µF ceramic capacitor. 3, 5, 8, 11, 14, 25, 28, 31, 34, 36 GND / TMDS_GND N/A GND reference. Note 1: These 2 pins need to be connected together in-line on the PCB. See recommended layout diagram. Note 2: This output can be connected to an external 0.1 µF ceramic capacitor/pads to maintain backward compatibility with the CM2020. Note 3: Standard IEC 61000-4-2, C DISCHARGE=150pF, R DISCHARGE=330Ω, 5V_SUPPLY and LV_SUPPLY within recommended operating conditions, GND=0V, 5V_OUT (pin 38), and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1 µF ceramic capacitor connected to GND. Note 4: Human Body Model per MIL-STD-883, Method 3015, C DISCHARGE=100pF, RDISCHARGE=1.5kΩ, 5V_SUPPLYand LV_SUPPLY within recommended operating conditions, GND=0V, 5V_OUT (pin 38), and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1 µF ceramic capacitor connected to GND. Note 5: These pins should be routed directly to the associated GND pins on the HDMI connector with single point ground vias at the connector. Note 6: The slew-rate control and active acceleration circuitry dynamically offsets the system capacitive load on these pins. |
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Similar Description - CM2030 |
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