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MC68HC05J3CP Datasheet(PDF) 11 Page - Motorola, Inc |
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MC68HC05J3CP Datasheet(HTML) 11 Page - Motorola, Inc |
11 / 92 page MC68HC05J3 MOTOROLA v Figure Number Page Number TITLE LIST OF FIGURES 1-1 MC68HC05J3 block diagram..................................................................................1-2 2-1 RAM bootloader circuit ...........................................................................................2-2 2-2 20-pin SOIC/DIP single chip and bootloader mode pin assignments.....................2-3 2-3 Oscillator connections ............................................................................................2-5 2-4 STOP and WAIT flowcharts ....................................................................................2-8 3-1 Memory map of the MC68HC05J3 .........................................................................3-2 4-1 Standard I/O port structure.....................................................................................4-2 4-2 Port B keyboard interrupt function ..........................................................................4-3 4-3 Port logic levels.......................................................................................................4-6 5-1 Core timer block diagram........................................................................................5-1 6-1 16-bit programmable timer block diagram ..............................................................6-2 6-2 Timer state timing diagram for reset .......................................................................6-9 6-3 Timer state timing diagram for input capture ..........................................................6-9 6-4 Timer state timing diagram for output compare ......................................................6-10 6-5 Timer state timing diagram for timer overflow.........................................................6-10 7-1 Reset timing diagram..............................................................................................7-1 7-2 Interrupt flow chart..................................................................................................7-5 8-1 Programming model ...............................................................................................8-1 8-2 Stacking order ........................................................................................................8-1 9-1 Equivalent test load ................................................................................................9-2 9-2 External interrupt timing .........................................................................................9-6 10-1 20-pin SOIC pinout ...............................................................................................10-1 10-2 20-pin PDIP pinout ...............................................................................................10-1 10-3 20-pin SOIC mechanical dimensions ...................................................................10-2 10-4 20-pin PDIP mechanical dimensions....................................................................10-3 TPG 8 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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