NCP3127 datasheet(8/24 Pages) ONSEMI

Part #	NCP3127

Description	2 A Synchronous PWM Switching Converter

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NCP3127

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8

source of 10

mA (typ), which charges the external integrator

capacitor of the OTA. Figure 14 is a typical soft−start

sequence. The sequence begins once VIN and VBST surpass

their UVLO thresholds and OCP programming is complete.

The current sourced out of the COMP pin continually

increases the voltage until regulation is reached. Once the

voltage reaches 400 mV logic is enabled. When the voltage

exceeds 900 mV, switching begins. Current is sourced out of

the COMP pin, placing the regulator into open loop

operation until 800 mV is sensed at the FB pin. Once

800 mV is sensed at the FB pin, open loop operation ends

and closed loop operation begins. In closed loop operation,

the OTA is capable of sourcing and sinking 120

mA.

Figure 18. Soft−Start Sequence

VCC

COMP

VFB

BG

TG

BG Comparator

BG Comparator Output

Vout

UVLO POR

Delay

Current

COMP

Delay

Soft−Start Normal Operation

UVLO

0.9 V

3.85 V

4.2 V

DAC Voltage

500 mV

50 mV

Trip Set

Overcurrent Threshold Setting

NCP3127 overcurrent threshold can be set from 50 mV to

550 mV, by adding a resistor (RSET) between ISET and

GND. During a short period of time following VIN rising

over UVLO threshold, an internal 10

mA current (IOCSET) is

sourced from the ISET pin, creating a voltage drop across

RSET. The voltage drop is compared against a stepped

internal voltage ramp. Once the internal stepped voltage

reaches the RSET voltage, the value is stored internally until

power is cycled. The overall time length for the OC setting

procedure is approximately 9 ms. Connecting an RSET

resistor between ISET and GND, the programmed threshold

will be:

IOCth +

IOCSET *RSET

RDS(on)

³ 2.0 A +

10 mA*21 kW

105 mW

(eq. 1)

IOCSET = Sourced current

IOCth = Current trip threshold

RDS(on) = On resistance of the low side MOSFET

RSET = Current set resistor

The RSET values range from 5 kW to 55 kW. If RSET is not

connected, the device switches the OCP threshold to a fixed

375 mV value (3.57 A), an internal safety clamp on ISET is

triggered as soon as ISET voltage reaches 700 mV, enabling

the 375 mV fixed threshold and ending the OCP setting

period. The current trip threshold tolerance is

$25 mV. The

accuracy is best at the highest set point (550 mV). The

accuracy will decrease as the set point decreases.

MOSFET tolerances with temperature and input voltage

will vary the over current set threshold operating point. A

graph of the typical current limit set thresholds at 4.5 V and

12 V is shown in Figure 19.

RSET (kW)

Figure 19. RSET Value for Output Current

5.0 V

12 V

0

0.5

1

1.5

2

2.5

3

3.5

4

5

1015

202530

Current Limit Protection

In case of a short circuit or overload, the low−side (LS)

FET will conduct large currents. The regulator will latch off,

protecting the load and MOSFETs from excessive heat and

damage. Low−side RDS(on) sense is implemented at the end

of each LS−FET turn−on duration to sense the current.

While the low side MOSFET is on, the VSW voltage is

compared to the user set internally generated OCP trip

voltage. If the VSW voltage is lower than OCP trip voltage,

an overcurrent condition occurs and a counter counts

consecutive current trips. If the counter reaches 7, the PWM

logic and both HS−FET and LS−FET are turned off. The

regulator has to go through a Power On Reset (POR) cycle

to reset the OCP fault as shown in Figure 20.

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