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CDCLVP111RHBT Datasheet(PDF) 2 Page - Texas Instruments |
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CDCLVP111RHBT Datasheet(HTML) 2 Page - Texas Instruments |
2 / 15 page CLK_SEL VBB 30 31 29 28 27 26 23 22 24 21 20 19 18 17 15 14 13 12 11 10 5 CLK0 CLK0 CLK1 CLK1 0 1 3 4 6 7 2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q0 Q1 Q2 Q3 Q4 Q5 Q7 Q6 Q9 Q8 + + - - - - - CDCLVP111 SCAS859D – JANUARY 2009 – REVISED MARCH 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DEVICE INFORMATION PIN FUNCTIONS(1) PIN DESCRIPTION NAME NO. Clock select. Used to select between CLK0 and CLK1 input pairs. LVTTL/LVCMOS functionality CLK_SEL 2 compatible. CLK0, CLK0 3, 4 Differential LVECL/LVPECL input pair CLK1, CLK1 6, 7 11, 13, 15, 18, Q [9:0] 20, 22, 24, 27, LVECL/LVPECL clock outputs, these outputs provide low-skew copies of CLKn. 29, 31 10, 12, 14, 17, Q[9:0] 19, 21,23, 26, LVECL/LVPECL complementary clock outputs, these outputs provide copies of CLKn. 28, 30 VBB 5 Reference voltage output for single-ended input operation VCC 1, 9, 16, 25, 32 Supply voltage VEE 8 Device ground or negative supply voltage in ECL mode The PowerPAD of the QFN32 and LQFP package is thermally connected to the die to improve the heat PowerPAD™ 0 transfer out of the package. The pad of the LQFP with PowerPAD must be left floating or connected to VEE. The pad of the QFN32 with PowerPAD must be connected to VEE. (1) CLKn, CLK_SEL pull down resistor = 75 k Ω; CLKn pull up resistor = 37.5 kΩ; CLKn pull down resistor = 50 kΩ. 2 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :CDCLVP111 |
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