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DESCRIPTION/ORDERING INFORMATION (CONTINUED)

P82B96

DUAL BIDIRECTIONAL BUS BUFFER

SCPS144B – MAY 2006 – REVISED JULY 2007

One of the advantages of the P82B96 is that it can isolate bus capacitance such that the total loading (devices

devices in a system, or the physical separation between them, are virtually eliminated.

The P82B96 easily can transmit SDA/SCL signals via balanced transmission lines (twisted pairs) or with

galvanic isolation (optocoupling), because separate directional Tx and Rx signals are provided. The Tx and Rx

signals may be connected directly (without causing bus latching), to provide an alternative bidirectional signal

Two or more Sx or Sy I/Os must not be interconnected. The P82B96 design does not support this configuration.

propagated to Sx/Sy as a buffered low with a slightly higher voltage level. If this special buffered low is applied

not propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to similar buffers that rely

on special logic thresholds for their operation, such as the PCA9515A.

slave devices or Tx/Rx signals of a second P82B96, if required. The Tx/Rx and Ty/Ry I/O pins use the standard

line. Similarly, if Ry and Ty are connected, Sy can function as either the SDA or SCL line. There are no

restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or

multi-point configuration with the Tx/Rx and Ty/Ry I/O pins on the common bus, and the Sx/Sy side connected

to the line-card slave devices.

TERMINAL FUNCTIONS

NO.

NAME

DESCRIPTION

1

Sx

2

Rx

3

Tx

4

GND

Ground

5

Ty

6

Ry

7

Sy

8

Supply voltage

2

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