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P82B96DGKR Datasheet(PDF) 5 Page - Texas Instruments |
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P82B96DGKR Datasheet(HTML) 5 Page - Texas Instruments |
5 / 28 page www.ti.com Electrical Characteristics P82B96 DUAL BIDIRECTIONAL BUS BUFFER SCPS144B – MAY 2006 – REVISED JULY 2007 VCC = 2.3 V to 2.7 V, voltages are specified with respect to GND (unless otherwise noted) TA = 25°C TA = –40°C to 85°C TEST PARAMETER UNIT CONDITIONS MIN TYP(1) MAX MIN MAX Temperature coefficient of ΔV/ΔTIN Sx, Sy –2 mV/ °C input thresholds ISx, ISy = 3 mA 0.8 0.88 1 VOL Low-level output voltage Sx, Sy (2)V ISx, ISy = 0.2 mA 0.67 0.73 0.79 (2) Temperature coefficient of ΔV/ΔTOUT Sx, Sy ISx, ISy = 0.2 mA –1.8 mV/ °C output low levels(3) ICC Quiescent supply current Sx = Sy = VCC 0.9 1.8 2 mA Additional supply current ΔICC Tx, Ty 1.7 2.75 3 mA per pin low Dynamic output sink VSx, VSy > 2 V, 7 18 5.5 mA capability on I2C bus VRx, VRy = low IIOS Sx, Sy VSx, VSy = 2.5 V, Leakage current on I2C bus 0.1 1 1 μA VRx, VRy = high VTx, VTy > 1 V, Dynamic output sink Tx, Ty VSx, VSy = low on 60 100 60 mA capability on buffered bus I2C bus = 0.4 V IIOT VTx, VTy = VCC = Leakage current 2.5 V, 0.1 1 1 μA on buffered bus VSx, VSy = high Bus low, VRx, Input current from I2C bus Sx, Sy –1 1 VRy = high Input current Bus low, VRx, II –1 1 μA from buffered bus VRy = 0.4 V Rx, Ry Leakage current VRx, VRy = VCC 1 1.5 on buffered bus input Input logic level high threshold(4) 0.65 0.7 (2) on normal I2C bus Sx, Sy Input logic level low threshold(4) 0.6 0.65 (2) VIT Input threshold V on normal I2C bus Input logic level high 0.58 VCC 0.58 VCC Rx, Ry Input threshold 0.5 VCC Input logic level low 0.42 VCC 0.42 VCC (VSx output low Input/output logic level at 3 mA) – VIOdiff Sx, Sy 100 150 100 mV difference(5) (VSx input high max) for I2C applications Sx, Sy are low, VCC VCC voltage at which all Sx, Sy ramping, voltage on VIOrel 1 1 V buses are released Tx, Ty Tx, Ty lowered until released Temperature coefficient of release ΔV/ΔTREL –4 mV/ °C voltage Cin Input capacitance Rx, Ry 2.5 4 4 pF (1) Typical value is at VCC = 2.5 V, TA = 25°C (2) See the Typical Characteristics section of this data sheet. (3) The output logic low depends on the sink current. (4) The input logic threshold is independent of the supply voltage. (5) The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for VSX output low always exceeds the minimum VSx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device. While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another P82B96, this has no consequences for normal applications. In any design, the Sx pins of different devices should never be linked, because the resulting system would be very susceptible to induced noise and would not support all I2C operating modes. 5 Submit Documentation Feedback |
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