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PCA9555DB Datasheet(PDF) 5 Page - Texas Instruments |
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PCA9555DB Datasheet(HTML) 5 Page - Texas Instruments |
5 / 35 page VCC CLK D Q FF Configuration Register Data From Shift Register Data From Shift Register Q Write Configuration Pulse CLK D Q FF Q Write Pulse Output Port Register 100 kW Q1 Q2 GND I/O Pin Output Port Register Data CLK D Q FF Q Input Port Register Read Pulse CLK D Q FF Q Polarity Inversion Register Write Polarity Pulse Input Port Register Data Polarity Register Data To INT Data From Shift Register I/O Port PCA9555 www.ti.com ......................................................................................................................................................... SCPS131E – AUGUST 2005 – REVISED MAY 2008 SIMPLIFIED SCHEMATIC OF P-PORT I/Os(1) (1) At power-on reset, all registers return to default values. When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be raised above VCC to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation. Copyright © 2005–2008, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): PCA9555 |
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