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ADS5400IPZPR Datasheet(PDF) 6 Page - Texas Instruments |
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ADS5400IPZPR Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 50 page  ADS5400 SLAS611B – OCT 2009 – REVISED MARCH 2010 www.ti.com SWITCHING CHARACTERISTICS (continued) Typical values at TA = 25°C, Min and Max values over full temperature range TMIN = –40°C to TMAX = 85°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS/NOTES MIN TYP MAX UNIT DIGITAL INPUTS (SCLK, SDIO, SDENB) VIH High level input voltage 2 AVDD3 + 0.3 V VIL Low level input voltage 0 0.8 V IIH High level input current ±1 mA IIL Low level input current ±1 mA CIN Input capacitance 2 pF DIGITAL INPUTS ( ENEXTREF, ENPWD, ENA1BUS) VIH High level input voltage 2 AVDD5 + 0.3 V VIL Low level input voltage 0 0.8 V IIH High level input current 125 mA ~40k Ω internal pull-down IIL Low level input current 20 mA CIN Input capacitance 2 pF DIGITAL OUTPUTS (SDIO, SDO) VOH High level output voltage IOH = 250 µA 2.8 V VOL Low level output voltage IOL = 250 µA 0.4 V CLOCK INPUTS RIN Differential input resistance CLKINP, CLKINN 130 160 190 Ω Input capacitance Estimated to ground from each CIN CLKIN pin, excluding soldered 0.8 pF packaged TIMING CHARACTERISTICS (1) Typical values at TA = 25°C, Min and Max values over full temperature range TMIN = –40°C to TMAX = 85°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS/NOTES MIN TYP MAX UNIT ta Aperture delay 250 ps Uncertainty of sample point due to internal jitter Aperture jitter, rms 125 fs sources Bus A, using Single Bus Mode 7 Bus A, using Dual Bus Mode Aligned 7.5 Latency Cycles Bus B, using Dual Bus Mode Aligned 8.5 Bus A and B, using Dual Bus Mode Staggered 7.5 LVDS OUTPUT TIMING (DATA, CLKOUT, OVR/SYNCOUT)(2) tCLK Clock period 1 10 ns tCLKH Clock pulse duration, high Assuming worst case 45/55 duty cycle 0.45 ns tCLKL Clock pulse duration, low Assuming worst case 55/45 duty cycle 0.45 ns tPD-CLKDIV2 Clock propagation delay CLKIN rising to CLKOUT rising in divide by 2 mode 700 1200 1700 ps tPD-CLKDIV4 Clock propagation delay CLKIN rising to CLKOUT rising in divide by 4 mode 700 1200 1700 ps Bus A data propagation tPD-ADATA 700 1400 2100 ps delay CLKIN falling to Data Output transition Bus B data propagation tPD-BDATA 700 1400 2100 ps delay (1) Timing parameters are specified by design or characterization, but not production tested. (2) LVDS output timing measured with a differential 100 Ω load placed ~4 inches from the ADS5400. Measured differential load capacitance is 3.5pF. Measurement probes and other parasitics add ~1pF. Total approximate capacitive load is 4.5pF differential. All timing parameters are relative to the device pins, with the loading as stated. 6 Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS5400 |
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